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cyw4354 single-chip 5g wi-fi ieee 802.11ac 22 mac/baseband/radio with integrated bluetooth 4.1 and fm receiver cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-14809 rev. *j revised wednesday, september 28, 2016 the cypress cyw4354 is a complete dual?band (2.4 ghz and 5 ghz) 5g wi?fi 2 2 mimo ? mac/phy/radio system?on?a?chip. this wi?fi single?chip device provides a high level of integratio n with dual?stream ieee 802.11ac mac/baseband/radio, bluetooth 4.1, and fm radio receiver. in ieee 802.11ac mode, the wlan ope ration supports rates of mcs0?mcs9 (up to 256 qam) in 20 mhz, 40 mhz, and 80 mhz channels for data rates up to 867 mbps. in addition, all the rates specifie d in ieee 802.11a/b/g/n are suppor ted. included on?chip are 2.4 ghz and 5 ghz transmit power amplifiers and receive low noise amplifiers. for the wlan section, several alternative host interface options are included: an sdio v3.0 inte rface that can operate in 4b or 1b modes, a high-speed inter-chip (hsic) interface, and a pcie v3.0 compliant interface running at gen1 speeds. for the bluetooth section, host interface options of a high-speed 4- wire uart and usb 2.0 full-speed (12 mbps) are provided. the cyw4354 uses advanced design techniques and process technolo gy to reduce active and idle power, and includes an embedded power management unit that simpli fies the system power topology. in addition, the cyw4354 implements highly sophisticated enhanc ed collaborative coexistence hardware mechanisms and algorithms that ensure that wlan and bluet ooth collaboration is optimized for maximum perfo rmance. coexistence support for external radios (such as lte cellular and gps) is provided via an external in terface. as a result, enhanced overall quality for simultaneous vo ice, video, and data transmission on a handheld system is achieved. cypress part numbering scheme cypress is converting the acquired iot part nu mbers from broadcom to the cypress part numbering scheme. due to this conversion, there is no change in form, fit, or functi on as a result of offering the device with cypress part number marking. the table pro vides cypress ordering part number that matches an existing iot part number. table 1. mapping table for part number between broadcom and cypress broadcom part number cypress part number BCM4354 cyw4354 BCM4354xkubg cyw4354xkubg BCM4354xkwbg cyw4354xkwbg BCM4354zkubg cyw4354zkubg
document number: 002-14809 rev. *j page 2 of 165 cyw4354 features ieee 802.11x key features ieee 802.11ac draft compliant. dual?stream spatial multiplexing up to 867 mbps data rate. supports 20, 40, and 80 mhz channels with optional sgi (256 qam modulation). full ieee 802.11a/b/g/n lega cy compatibility with enhanced performance. tx and rx low?density parity check (ldpc) support for improved range and power efficiency. supports ieee 802.11ac/n beamforming. on?chip power amplifiers and low?noise amplifiers for both bands. supports various rf front?end architectures including: ? two antennas with one each dedicated to bluetooth and wlan. ? two antennas with wlan dive rsity and a shared bluetooth antenna. shared bluetooth and wlan receive signal path eliminates the need for an external power splitter while maintaining excellent sensitivity for both bluetooth and wlan. internal fractional npll allows support for a wide range of reference clock frequencies supports ieee 802.15.2 external coexistence interface to optimize bandwidth utilization wit h other co?located wireless. technologies such as lte or gps. supports standard sdio v3.0 (up to sdr104 mode at 208 mhz, 4?bit and 1-bit) host interfaces. backward compatible with sdio v2.0 host interfaces. alternative host interface supports hsic v1.0 pcie mode complies with pci express base specification revision 3.0 for 1 lane and power management running at gen1 speeds. integrated armcr4? processor with tightly coupled memory for complete wlan subsystem fu nctionality, mi nimizing the need to wake up the applications processor for standard wlan functions. this allows for further minimization of power consumption, while maintaining t he ability to field upgrade with future features. on?chip memory includes 768 kb sram and 640 kb rom. onedriver? software architec ture for easy migration from existing embedded wlan and bluetooth devices as well as future devices. bluetooth and fm key features complies with bluetooth core sp ecification version 4.1 with provisions for supporting future specifications. bluetooth class 1 or class 2 transmitter operation. supports extended synchronous connections (esco), for enhanced voice quality by allowing for retransmission of dropped packets. adaptive frequency hopping (afh) for reducing radio frequency interference. interface support, host controll er interface (hci) using a usb or high?speed uart interface and pcm for audio data. usb 2.0 full?speed (12 mbps) supported for bluetooth. the fm unit supports hci for communication. low power consumption improves battery life of handheld devices. fm receiver: 65 mhz to 108 mhz fm bands; supports the european radio data systems ( rds) and the north american radio broadcast data system (rbds) standards. supports multiple simultaneous advanced audio distribution profiles (a2dp) for stereo sound. automatic frequency detection for standard crystal and tcxo values. supports serial flash interfaces. general features supports battery range from 3.0v to 5.25v supplies with internal switching regulator. programmable dynamic power management 484 bytes of user-accessible otp for storing board parameters gpios: 11 in wlbga, 16 in wlcsp package options: ? 192-ball wlbga (4.87 mm 7.67 mm, 0.4 mm pitch ? 395-bump wlcsp (4.87 mm 7.67 mm, 0.2 mm pitch) security: ? wpa? and wpa2? (personal) support for powerful encryp- tion and authentication ? aes and tkip in hardware for faster data encryption and ieee 802.11i compatibility ? reference wlan subsystem provides cisco ? compatible extensions (ccx, ccx 2.0, ccx 3.0, ccx 4.0, ccx 5.0) ? reference wlan subsystem prov ides wi-fi protected setup (wps) worldwide regulatory support: global products supported with worldwide homologated design.
document number: 002-14809 rev. *j page 3 of 165 cyw4354 figure 1. functional block diagram iot resources cypress provides a wealth of data at http://www.cypress.com /internet-things-iot to help you to select th e right iot device for your design, and quickly and effectively integrate the device into your design. cypress provides customer access to a wide range of information, including technical documentat ion, schematic diagrams, product bill of ma terials, pcb layout information, and soft ware updates. customers can acquire technica l documentation and soft ware from the cypress support community website ( http://community.cypress.com/ ) t/r ? switch diplexer vio vbat 5g ? wlan 2g ? wlan fm ? rx wlan ? host ? i/f bluetooth ? host ? i/f ? fm ? rx ? host ? i/f wl_reg_on sdio pcie bt_reg_on uart bt_dev_wake bt_host_wake i 2 s clk_req fm ? audio ? out i 2 s hsic pcm coex external ? coexistence ? i/f fm ? i/f usb ? 2.0 2.g ? wl/bt ? rx bt ? tx t/r ? switch 5g ? wlan t/r ? switch 3pst ? switch 2g ? wlan ? tx ant1 diplexer ant0 cyw4354
document number: 002-14809 rev. *j page 4 of 165 cyw4354 contents 1. overview ........................................................................ 6 1.1 overview ............................................................... 6 1.2 features ................................................................ 8 1.3 standards compliance .......................................... 9 2. power supplies an d power management ................. 10 2.1 power supply topology ...................................... 10 2.2 cyw4354 pmu features . .............. .............. ....... 10 2.3 wlan power management.. .............. ........... ...... 12 2.4 pmu sequencing .............. .............. .............. ...... 12 2.5 power-off shutdown ........................................... 13 2.6 power-up/power-down/rese t circuits ............... 13 3. frequency references ............................................... 14 3.1 crystal interface and clock generation .............. 14 3.2 external frequency refer ence ............................ 15 3.3 external 32.768 khz low-power oscillator ......... 17 4. bluetooth + fm subsystem overview ...................... 18 4.1 features .............................................................. 18 4.2 bluetooth radio................................................... 19 5. bluetooth baseband core ... .............. .............. .......... 21 5.1 bluetooth 4.1 features ........................................ 21 5.2 bluetooth low energy ......................................... 21 5.3 link control layer ............................................... 21 5.4 test mode support ........... .............. .............. ....... 22 5.5 bluetooth power management unit ......... ............ 22 5.6 adaptive frequency hoppin g .............................. 26 5.7 advanced bluetooth/wlan coexistence ............ 27 5.8 fast connection (interlaced page and inquiry scans)................................................................... 27 6. microprocessor and memory unit for bluetooth ..... 28 6.1 ram, rom, and patch memory .......................... 28 6.2 reset ................................................................... 28 7. bluetooth peripheral transport unit ........................ 29 7.1 spi interface ........................................................ 29 7.2 spi/uart transport detection ........................... 29 7.3 pcm interface ..................................................... 29 7.4 usb interface ...................................................... 37 7.5 uart interface.................................................... 39 7.6 i 2 s interface ........................................................ 41 8. fm receiver subsystem ............................................ 44 8.1 fm radio ............................................................. 44 8.2 digital fm audio interfaces ................................. 44 8.3 fm over bluetooth .............................................. 44 8.4 esco ................................................................... 44 8.5 wide band speech link ...................................... 44 8.6 a2dp ................................................................... 44 8.7 autotune and search algo rithms ......................... 44 8.8 audio features .................................................... 45 8.9 rds/rbds .......................................................... 47 9. wlan global functions ............................................ 48 9.1 wlan cpu and memory subsystem ...... ............ 48 9.2 one-time programmable memory ...................... 48 9.3 gpio interface .................................................... 48 9.4 external coexistence interface ........................... 49 9.5 uart interface .................................................... 50 9.6 jtag interface .................................................... 50 9.7 sprom interface ................................................ 50 9.8 sflash interface ............................................... 50 10. wlan host interfaces .............................................. 51 10.1 sdio v3.0 .......................................................... 51 10.2 hsic interface .................................................. 53 10.3 pci express interface ....................................... 53 11. wireless lan mac and phy ............. .............. ........ 56 11.1 ieee 802.11ac draft mac .............. ........... ........ 56 11.2 ieee 802.11ac draft phy .............. ........... ........ 59 12. wlan radio subsystem ..... .............. .............. ........ 61 12.1 receiver path .................................................... 61 12.2 transmit path .................................................... 61 12.3 calibration ......................................................... 62 13. pinout and signal descriptions .............................. 63 13.1 ball maps ........................................................... 63 13.2 pin lists ............................................................. 65 13.3 signal descriptions......... ................................... 82 13.4 wlan/bt gpio signals and strapping options 96 13.5 gpio alternative signal functions.................... 97 13.6 i/o states .......................................................... 99 14. dc characteristics ................................................. 102 14.1 absolute maximum rati ngs ............................. 102 14.2 environmental ratings .. .................................. 103 14.3 electrostatic discharge specifications ............ 103 14.4 recommended operating conditions and dc characteristics .......................................................... 104 15. bluetooth rf specifications .................................. 106 16. fm receiver specifications ................................... 112 17. wlan rf specifications ........................................ 116 17.1 introduction ...................................................... 116 17.2 2.4 ghz band general rf specifications ....... 116 17.3 wlan 2.4 ghz receiver performance specifications ................................................................. 117 17.4 wlan 2.4 ghz transmitter performance specifications ................................................................. 123 17.5 wlan 5 ghz receiver performance specifications ................................................................. 124 17.6 wlan 5 ghz transmitter performance specifications ................................................................. 131 18. internal regulator electri cal specifications ........ 132 18.1 core buck switching re gulator ....................... 132 18.2 3.3v ldo (ldo3p3) ....................................... 133 18.3 3.3v ldo (ldo3p3_b) ................................... 134 18.4 2.5v ldo (btldo2p5).... ............................... 135 18.5 cldo .............................................................. 136 18.6 lnldo ............................................................ 137 19. system power consumption ................................. 138 19.1 wlan current consumption ........................... 138 19.2 bluetooth and fm current consumption......... 140 20. interface timing and ac characteristics ............. 141 20.1 sdio timing ............... ..................................... 141 20.2 hsic interface specifications .......................... 150 20.3 pci express interface pa rameters.................. 151 20.4 jtag timing ................. ................................. 152 21. power-up sequence and timing ........................... 153
document number: 002-14809 rev. *j page 5 of 165 cyw4354 21.1 sequencing of reset and regulator control signals ............................................................... 153 22. package information .............................................. 157 22.1 package thermal characteristics ................... 157 22.2 junction temperature estimation and psi jt versus theta jc ............................................................ 157 22.3 environmental characteri stics ......................... 157 23. mechanical information ......................................... 158 24. ordering information .............................................. 162 document history ........................................................ 163
document number: 002-14809 rev. *j page 6 of 165 cyw4354 1. overview 1.1 overview the cypress cyw4354 single-chip device provides the highes t level of integration for a mobile or handheld wireless system, with integrated ieee 802.11 a/b/ g/n/ac mac/baseband/radio, bluetooth 4.1 + edr (enhanced data rate), and fm receiver. it provides a small form-f actor solution with minimal external co mponents to drive down cost for mass volumes and allows for handheld devic e flexibility in size, fo rm, and function. compre hensive power management circuitry and software ensure the system can meet the need s of highly mobile devices that require minimal power consumption and reliable operation. figure 2 on page 7 shows the interconnect of all the major physical blocks in the cyw4354 and their associated external interfaces, which are described in greater detail in the following sections. table 2. device options and features feature wlbga wlcsp package ball count 192 pins 395 bumps pcie yes yes usb2.0 (bluetooth) yes yes hsic yes yes i 2 s multiplexed onto six parallel flash pins no gpio 11 16 sdio 3.0 yes yes
document number: 002-14809 rev. *j page 7 of 165 cyw4354 figure 2. cyw4354 block diagram cyw4354 bt/fm fmrx debug btfm ? control ? clock ptu wlan pmu controller 5 ? ghz ? ipa 5 ? ghz 2.4 ? ghz diplexer bpf bpf lna core1 lna 5 ? ghz 2.4 ? ghz lna core1 shared ? lna bt ? rx radio 2x2 ? lcnxnphy 802.11abgn otp otp gpio uart jtag sw ? reg ldo lpo xtal ? osc por gpio jtag uart xtal power ? supply hsic pcie sdio arm jtag axi backplane ram rom bt \ wlan ? eci io ? port ? control uart slimbus debug ? uart meif i 2 s/pcm1 i 2 s/pcm2 gpio wake/sleep control gnss ? lna ? ant ? control clock ? management sleep timer pmu pmu ? controller lpo xo ? buffer por bt ? phy bt ? rf ram rom patch inter ? ctrl dma bus ? arb wd ? timer sw ? timer gpio ? ctrl apb ahb ahb2 ? apb ? bridge cortex ? m3 etm jtag sdp ahb ? bus ? matrix clb ahb fm ? digital fm ? rf fm ? rx bt ? digital ? io bt ? tx ext ? lna ? rf ? switch ? control *sdio ? or ? *pcie ? 2.0 ? jtag smps ? control xtal vbat vreg por 2.4 ? ghz ? ipa 5 ? ghz ? ipa 2.4 ? ghz ? ipa diplexer bpf bpf coex
document number: 002-14809 rev. *j page 8 of 165 cyw4354 1.2 features the cyw4354 supports the following features: ieee 802.11a/b/g/n/ac dual-band 2x2 mimo radio with virtual-simultaneous dual-band operation bluetooth v4.1 + edr with integrated class 1 pa concurrent bluetooth, fm (rx) rds/rbds, and wlan operation on-chip wlan driver execution capabl e of supporting ieee 802.11 functionality single- and dual-antenna support ? single antenna with shared lna ? simultaneous bt/wlan receive with single antenna wlan host interface options: ? sdio v3.0 (1-bit/4-bit)?up to 20 8 mhz clock rate in sdr104 mode ? hsic (usb device interface for sh ort distance on-board applications) ? pcie 2.0 bt host digital interface (can be used concurrently with above interfaces): ? uart (up to 4 mbps) bt supports full-speed usb 2.0-compliant interface eci?enhanced coexistence support, ability to coordi nate bt sco transmissions around wlan receives i 2 s/pcm for fm/bt audio, hci for fm block control hci high-speed uart (h4, h4+, h5) transport support wideband speech support (16 bits linear data, msb first, left just ified at 4k samples/s for transparent air coding, both throug h i 2 s and pcm interface) bluetooth smartaudio ? technology improves voice and music quality to headsets bluetooth low power inquiry and page scan bluetooth low energy (ble) support bluetooth packet loss concealment (plc) bluetooth wide band speech (wbs) fm advanced internal antenna support fm auto search/tuning functions fm multiple audio routing options: i 2 s, pcm, esco, and a2dp fm mono-stereo blend and switch , and soft mute support fm audio pause detect support audio rate-matching algorithms multiple simultaneous a2dp audio stream fm over bluetooth operation and on- chip stereo headset emulation (sbc)
document number: 002-14809 rev. *j page 9 of 165 cyw4354 1.3 standards compliance the cyw4354 supports the following standards: bluetooth 2.1 + edr bluetooth 3.0 + hs bluetooth 4.1 (bluetooth low energy) 65 mhz to 108 mhz fm bands (us, europe, and japan) ieee802.11ac mandatory and optional requirements for 20 mhz, 40 mhz, and 80 mhz channels ieee 802.11n?handheld device class (section 11) ieee 802.11a ieee 802.11b ieee 802.11g ieee 802.11d ieee 802.11h ieee 802.11i security: ? wep ? wpa? personal ? wpa2? personal ? wmm ? wmm-ps (u-apsd) ? wmm-sa ? aes (hardware accelerator) ? tkip (hw accelerator) ? ckip (sw support) proprietary protocols: ? ccxv2 ? ccxv3 ? ccxv4 ? ccxv5 ieee 802.15.2 coexistence compliance?on silicon so lution compliant with ieee 3 wire requirements the cyw4354 will support the follo wing future drafts/standards: ieee 802.11r?fast roaming (between aps) ieee 802.11w?secure management frames ieee 802.11 extensions: ? ieee 802.11e qos enhancements (in accordance with the wmm ? specification, qos is already supported.) ? ieee 802.11h 5 ghz extensions ? ieee 802.11i mac enhancements ? ieee 802.11k radio resource measurement
document number: 002-14809 rev. *j page 10 of 165 cyw4354 2. power supplies and power management 2.1 power supply topology one buck regulator, multiple ldo regulators, and a power management unit (pmu) are integrated into the cyw4354. all regulators are programmable via the pmu. these blocks simplify power supply design for bluetooth, wlan, and fm functions in embedded designs. a single vbat (3.0v to 5.25v dc max.) and vio supply (1.8v to 3.3v ) can be used, with all additional voltages being provided by the regulators in the cyw4354. two control signals, bt_reg_on and wl_reg _on, are used to power-up the regulators an d take the respective section out of reset. the cbuck cldo and lnldo power up when any of the rese t signals are deasserted. all regulators are powered down only when both bt_reg_on and wl_reg_on are deasserted. the cldo and lnldo may be turned off/on based on the dynamic demands of the digital baseband. the cyw4354 allows for an extremely low power-consumption mode by completely shutting down the cbuck, cldo, and lnldo regulators. when in this state, lpldo1 (which is a low-power linear regulator supplied by the sy stem vio supply) provides the cyw4354 with all the voltages it requ ires, further reducing leakage currents. 2.2 cyw4354 pmu features vbat to 1.35vout (600 ma maximum) co re-buck (cbuck) switching regulator vbat to 3.3vout (600 ma maximum) ldo3p3 vbat to 3.3vout (150 ma maximum) ldo3p3_b vbat to 2.5v out (70 ma maximum) btldo2p5 1.35v to 1.2vout (150 ma maximum) lnldo 1.35v to 1.2vout (300 ma maximum) cldo with bypass mode for deep-sleep additional internal ldos (not externally accessible) figure 3 on page 11 illustrates the typical power topology for the cyw4 354. the shaded areas are internal to the cyw4354.
document number: 002-14809 rev. *j page 11 of 165 cyw4354 figure 3. typical power topology for the cyw4354 internal ? lnldo wl ? rf ? ?afe wl ? rf ? ?tx ? (2.4 ? ghz, ? 5 ? ghz) wl ? rf ? ?logen ? (2.4 ? ghz, ? 5 ? ghz) wl ? rf ? ?rx/lna ? (2.4 ? ghz, ? 5 ? ghz) wl ? rf ? ?xtal wl ? rf ? ?rfpll ? pfd/mmd bt ? rf/fm bt ? class ? 1 ? pa wl ? pad ? (2.4 ? ghz, ? 5 ? ghz) vddio_rf wl ? otp ? 3.3v wl ? rf ? ?vco wl ? rf ? ?cp internal ? lnldo internal ? vcoldo internal ? lnldo xtal ? ldo 1.2v 1.2v 1.2v 1.2v 1.2v lnldo max ? 150 ? ma hsic/dfe/dfll pcie ? pll/rxtx wlan ? bbpll/dfll wlan/bt/clb/top, ? always ? on wl ? otp wl ? phy wl ? digital bt ? digital wl/bt ? srams cldo max ? 300 ? ma (bypass ? in ? deep ? sleep) 1.2v? 1.1v btldo2p5 max ? 70 ? ma 2.5v internal ? lnldo internal ? lnldo ldo3p3_b max ? 150 ? ma 2.5v 2.5v 3.3v 1.2v 1.35v wl_reg_on bt_reg_on lpldo1 3 ? ma core ? buck ? regulator cbuck max ? 600 ? ma 1.1v vddio vbat wl ? rf \ pa ? (2.4g, ? 5g) ldo3p3 max ? 600 ? ma 3.3v
document number: 002-14809 rev. *j page 12 of 165 cyw4354 2.3 wlan power management the cyw4354 has been designed with the stringen t power consumption requirements of mobile devices in mind. all areas of the chi p design are optimized to minimize power c onsumption. silicon processes and cell librari es were chosen to reduce leakage current and supply voltages. additionally, the cyw4354 integrated ram is a high vt memory with dynamic clock control. the dominant supply current consumed by the ram is leakage current only. additiona lly, the cyw4354 includes an advanced wlan power management unit (pmu) sequencer. the pmu sequencer provides significant power savings by putting the cyw4354 into various power management states appropriate to the current environment and activities that are bei ng performed. the power management unit enables and disables internal regulators, switches, and other blocks based on a computation of the required resources and a tab le that describes the relationship between resources and the time needed to enable and disable them. power up sequences are fully programmable. configurable, free-running counte rs (running at 32.768 khz lpo clock) in the pmu sequencer are used to turn on/ turn off individual regulators and power switches. clock speeds are dynamically changed (or gat ed altogether) for the current m ode. slower clock speeds are used wherever possible. the cyw4354 wlan power states are described as follows: active mode? all wlan blocks in the cyw43 54 are powered up and fully functi onal with active carrier sensing and frame trans- mission and receiving. all required regulators are enabled and put in the most efficient mode based on the load current. clock speeds are dynamically adjusted by the pmu sequencer. deep-sleep mode?most of the chip including both analog and digita l domains and most of the regulators are powered off. all main clocks (pll, crystal oscillator, or tcxo) are shut down to reduce active power to the minimum. the 32.768 khz lpo clock is avail able only for the pmu sequencer. this condition is necessary to allow the pmu sequencer to wake up the chip and transition to active mode. logic states in the digital core ar e saved and preserved into a retention memo ry in the always-on domain before the digit al core is powered off. upon a wake-up event triggered by the pmu ti mers, an external interrupt or a host resume through the hsic or sdio bus, logic states in the digital core are restored to their pre-deep-sleep se ttings to avoid lengthy hw reinitializatio n. in deep- sleep mode, the primary source of pow er consumption is leakage current. power-down mode?the cyw4354 is effectively powered off by shutting down all internal regulators. the chip is brought out of this mode by external logic re-enabling the internal regulators. 2.4 pmu sequencing the pmu sequencer is responsible for minimizing system power consumption. it enables and disables various system resources based on a computation of the required resources and a table that describes the relationship between resources and the time nee ded to enable and disable them. resource requests may come from several sources: clock requests from cores, the minimum resources defined in the resourcemin register, and the resources requested by any active resource re quest timers. the pmu sequencer maps clock requests into a set o f resources required to pro duce the requested clocks. each resource is in one of four states : enabled, disabled, transition_on, and trans ition_off and has a timer that contains 0 wh en the resource is enabled or disabled and a non-zero value in the tran sition states. the timer is loaded with the time_on or time_off value of the resource when the pmu determines that the resource must be enabled or disabled. that timer decrements on each 32.768 khz pmu clock. when it reaches 0, the state changes from transition_off to disabled or tr ansition_on to enabled. if the time_on val ue is 0, the resource can go immediately from disabled to enabled. sim ilarly, a time_off value of 0 indicates that the resource can g o immediately from enabled to disabled. the terms enable sequence an d disable sequence refer to either the immediate transition o r the timer load-decrement sequence. during each clock cycle, t he pmu sequencer performs the following actions: computes the required resource set based on requests and the resource dependency table. decrements all timers whose values are non zero. if a timer re aches 0, the pmu clears the reso urcepending bit for the resource and inverts the resourcestate bit. compares the request with the current resource status and determines which re sources must be enabled or disabled. initiates a disable sequence for each resource that is enabl ed, no longer being requested, and has no powered up dependents. initiates an enable sequence for each resource that is disabled , is being requested, and has all of its dependencies enabled.
document number: 002-14809 rev. *j page 13 of 165 cyw4354 2.5 power-off shutdown the cyw4354 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other devices in the system, remain operational. when the cyw4354 is not needed in the system, vddio_rf and vddc are shut down while vddio remains powered. this allows the cyw4354 to be effectively off while keeping the i/o pins pow ered so that they do not dra w extra current from any other devices connected to the i/o. during a low-power shut-down state, provided vddio remains appli ed to the cyw4354, all outputs ar e tristated, and most inputs signals are disabled. input volta ges must remain within the limits defined for norma l operation. this is done to prevent curren t paths or create loading on any digital signals in the system, and enabl es the cyw4354 to be fully integrated in an embedded device an d take full advantage of the lowest power-savings modes. when the cyw4354 is powered on from this state, it is the same as a normal power-up and the device does not retain any informat ion about its state from bef ore it was powered down. 2.6 power-up/power -down/reset circuits the cyw4354 has two signals (see ta b l e 3 ) that enable or disable the bluetooth and wlan circuits and the internal regulator blocks, allowing the host to control power consumption. for timing diagra ms of these signals and the required power-up sequences, see power-up sequence and timing on page 153 . table 3. power-up/power-down/reset control signals signal description wl_reg_on this signal is used by the pmu (with bt_reg_on) to power up the wlan section. it is also or-gated with the bt_reg_on input to control the inter nal cyw4354 regulators. when this pin is high, the regulators are enabled and the wlan section is out of reset. when this pin is low, the wlan section is in reset. if bt_reg_on and wl_reg_on are both low, the regulators ar e disabled. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. bt_reg_on this signal is used by the pmu (with wl_reg_on) to decide whether or not to power down the internal cyw4354 regulators. if bt_reg_on and wl_reg_o n are low, the regulators will be disabled. this pin has an internal 200 k ? pull-down resistor that is enabled by def ault. it can be disabled through programming.
document number: 002-14809 rev. *j page 14 of 165 cyw4354 3. frequency references an external crystal is used for generating all radio frequencies and normal operation clocking. as an alternative, an external frequency reference may be used. in addition, a low-power oscillator (lpo) is provided for lower power mode timing. 3.1 crystal interface and clock generation the cyw4354 can use an external crystal to provide a frequency re ference. the recommended configuration for the crystal oscilla tor including all external components is shown in figure 4 . consult the reference schematics for the latest configuration. figure 4. recommended oscillator configuration a fractional-n synthesizer in the cyw4354 generates the radio fr equencies, clocks, and data/packet timing, enabling it to opera te using a wide selection of frequency references. for sdio, hsic, and pcie wlan host applications, the recommende d default frequency reference is a 37.4 mhz crystal. for pcie applications, see table 4 on page 15 for details on alternatives for the external fr equency reference. the signal characteristics for the crystal oscillator interface are also listed in ta b l e 4 . for sdio wlan host applications, the recomm ended default frequency reference is a 37.4 mhz crystal. the signal characteristics for the crystal oscillator interface are also listed in table 4 . note: although the fractional-n synthesizer can support alternative re ference frequencies, frequencies other than the default require support to be added in the driver, plus additional extensiv e system testing. contact broadcom for further details. wrf _xtal _out wrf _xtal _i n c* c* x ? ohms* *values ? determined ? by ? crystal ? drive ? level. ? see ? reference ? schematics ? for ? details. ? 37.4 ? mhz
document number: 002-14809 rev. *j page 15 of 165 cyw4354 3.2 external frequency reference for operation in sdio and hsic modes only, an alternative to a cr ystal (an external precision frequency reference) can be used. the recommended default frequency is 52 mhz 10 ppm, and it must meet the phase noise requirements listed in table 4 . if used, the external clock should be connected to the wrf_xta l_in pin through an external 1000 pf coupling capacitor, as shown in figure 5 . the internal clock buffer connected to this pin will be tu rned off when the cyw4354 goes into sleep mode. when the clock buffer turns on and off there will be a small impedance variation. power must be supplied to the wrf_xtal_vdd1p5 pin. figure 5. recommended ci rcuit to use with an external reference clock table 4. crystal oscillator and external clock?requirements and performance parameter conditions/notes crystal a external frequency ref- erence b,c min. typ. max. min. typ. max. units frequency 2.4g and 5g bands: ieee 802.11ac operation, sdio3.0, hsic and pcie wlan interfaces 35 37.4 ? ? 52 ? mhz 2.4g and 5g bands, ieee 802.11ac operation, pcie interface alternative frequency ?40????mhz 5g band: ieee 802.11n operation only 19 ? 52 35 ? 52 mhz 2.4g band: ieee 802.11n operation, and both bands legacy 802.11a/b/g operation only ranges between 19 mhz and 52 mhz d,e frequency tolerance over the lifetime of the equipment, including temperature f without trimming ?20 ? 20 ?20 ? 20 ppm crystal load capacitance? ?12????pf esr ? ??60??? ? drive level external crystal must be able to tolerate this drive level. 200?????w input impedance (wrf_xtal_in) resistive ???30100?k ? capacitive ? ? 7.5 ? ? 7.5 pf wrf_xtal_in input low level dc-coupled digital signal ???0?0.2v wrf_xtal_in input high level dc-coupled digital signal ???1.0?1.26v wrf_xtal_in input voltage (see figure 5 ) ac-coupled analog signal ? ? ? 400 ? 1200 mv p-p duty cycle 37.4 mhz clock ???405060% reference ? clock nc 1000 ? pf wrf_xtal_in wrf_xtal_out
document number: 002-14809 rev. *j page 16 of 165 cyw4354 phase noise g (ieee 802.11b/g) 37.4 mhz clock at 10 khz offset????? ?129 dbc/hz 37.4 mhz clock at 100 khz offset????? ?136 dbc/hz phase noise g (ieee 802.11a) 37.4 mhz clock at 10 khz offset????? ?137 dbc/hz 37.4 mhz clock at 100 khz offset????? ?144 dbc/hz phase noise g (ieee 802.11n, 2.4 ghz) 37.4 mhz clock at 10 khz offset????? ?134 dbc/hz 37.4 mhz clock at 100 khz offset????? ?141 dbc/hz phase noise g,h (ieee 802.11n, 5 ghz) 37.4 mhz clock at 10 khz offset????? ?142 dbc/hz 37.4 mhz clock at 100 khz offset????? ?149 dbc/hz phase noise g (ieee 802.11ac, 5 ghz) 37.4 mhz clock at 10 khz offset????? ?150 dbc/hz 37.4 mhz clock at 100 khz offset????? ?157 dbc/hz a. (crystal) use wrf_xtal_in and wrf_xtal_out. b. see ?external frequency reference? on page 15 for alternate connection methods. c. for a clock reference other than 37.4 mhz, 20 log10(f/ 37.4) db should be added to the limits, where f = the reference cloc k frequency in mhz. d. bt_tm6 should be tied low for a 52 mhz clock reference. for ot her frequencies, bt_tm6 should be tied high. note that 52 mhz i s not an auto?detected frequency using the lpo clock. e. the frequency step size is approximately 80 hz resolution. f. it is the responsibility of the equipment designer to select os cillator components that comply with these specifications. g. assumes that external clock has a flat phase noise response above 100 khz. h. if the reference clock frequency is <35 mhz the phase noise requirements must be tightened by an additional 2 db. table 4. crystal oscillator and external clock?requirements and performance (cont.) parameter conditions/notes crystal a external frequency ref- erence b,c min. typ. max. min. typ. max. units
document number: 002-14809 rev. *j page 17 of 165 cyw4354 3.3 external 32.768 khz low-power oscillator the cyw4354 uses a secondary low-frequency clock for low-power mode timing. either the internal low- precision lpo or an extern al 32.768 khz precision oscillator is required. the internal lpo fre quency range is approximately 33 kh z ( 30%) over process, volta ge, and temperature, which is adequate for some applications. however, one trade-off caused by this wide lpo tolerance is a small current consumption increase during power save mode that is incurred by the need to wake up earlier to avoid missing beacons. whenever possible, the preferred approach is to use a precision external 32.768 khz clock which meets the requirements listed i n ta b l e 5 . table 5. external 32.768 kh z sleep clock specifications parameter lpo clock unit nominal input frequency 32.768 khz frequency accuracy 200 ppm duty cycle 30?70 % input signal amplitude 200-3300 mv, p-p signal type square-wave or sine-wave ? input impedance a a. when power is applied or switched off. >100k ? <5 pf clock jitter (during initial start-up) < 10,000 ppm
document number: 002-14809 rev. *j page 18 of 165 cyw4354 4. bluetooth + fm subsystem overview the cypress cyw4354 is a bluetooth 4.1 + edr-compliant, baseband processor/2.4 gh z transceiver with an integrated fm/rds/ rbds receiver. it features the highest level of integration and el iminates all critical external components, thus minimizing th e footprint, power consumption, and system cost of a bluetooth plus fm radio solution. the cyw4354 is the optimal solution for any bluetooth voice and/or data application that also requires an fm radio receiver. th e bluetooth subsystem presents a st andard host controller interf ace (hci) via a high-speed uart and pcm for audio. the fm subsystem supports the hci control in terface, analog output, as well as i 2 s and pcm interfaces. the cyw4354 incorporates all bluetooth 4.1 features including secu re simple pairing, sniff subrating, and encryption pause and resume. the cyw4354 bluetooth radio transceiver provides enhanced radio performance to me et the most stringent mobile phone temperature applications and the tightest integration into mobile handsets and portable devices. it is fully compatible with an y of the standard tcxo frequencies and provides full radio compatibility to operate simultaneously with gps, wlan, and cellular radios. the bluetooth transmitter also features a cla ss 1 power amplifier with class 2 capability. 4.1 features major bluetooth features of the cyw4354 include: supports key features of upcoming bluetooth standards fully supports bluetooth core specification vers ion 4.1 + (enhanced data rate) edr features: ? adaptive frequency hopping (afh) ? quality of service (qos) ? extended synchronous connections (esco)?voice connections ? fast connect (interlaced page and inquiry scans) ? secure simple pairing (ssp) ? sniff subrating (ssr) ? encryption pause resume (epr) ? extended inquiry response (eir) ? link supervision timeout (lst) uart baud rates up to 4 mbps supports all bluetooth 4.1 packet types supports maximum bluetooth data rates over hci uart bt supports full-speed usb 2.0-compliant interface multipoint operation with up to seven active slaves ? maximum of seven simultaneous active acl links ? maximum of three simultaneous active sco and esco connections with scatternet support trigger broadcom fast connect (tbfc) narrowband and wideband packet loss concealment scatternet operation with up to four active pico nets with background scan and support for scatter mode high-speed hci uart transport support with low-power ou t-of-band bt_dev_wake and bt_host_wake signaling (see ?host controller power management? on page 23) channel quality driven data rate and packet type selection standard bluetooth test modes extended radio and production test mode features full support for po wer savings modes ? bluetooth clock request ? bluetooth standard sniff ? deep-sleep modes and software regulator shutdown tcxo input and auto-detection of all stand ard handset clock frequencies. also support s a low-power crystal, which can be used during power save mode for better timing accuracy.
document number: 002-14809 rev. *j page 19 of 165 cyw4354 major fm radio features include: 65 mhz to 108 mhz fm bands supported (us, europe, and japan) fm subsystem control using the bluetooth hci interface fm subsystem operates from reference clock inputs. improved audio interface capabilities with full-featured bidirectional pcm and i 2 s i 2 s can be master or slave. fm receiver-specific features include: excellent fm radio performance with 1 v sensitivity fo r 26 db (s+n)/n signal-dependent stereo/mono blending signal dependent soft mute auto search and tuning modes audio silence detection rssi, if frequency, status indicators rds and rbds demodulator and decoder with filter and buffering functions automatic frequency jump 4.2 bluetooth radio the cyw4354 has an integrated radio transceiv er that has been optimized for use in 2.4 ghz bluetooth wireless systems. it has b een designed to provide low-power, low-cost, robust communications for applications operating in the globally available 2.4 ghz unlicensed ism band. it is fully compliant with the bluetooth radio specification and edr specification and meets or exceeds th e requirements to provide the highest communication link quality of service. 4.2.1 transmit the cyw4354 features a fully integrated ze ro-if transmitter. the baseband transmit data is gfsk-modulated in the modem block and upconverted to the 2.4 ghz ism band in the transmitter path. the transmitter path consists of signal filtering, i/q upconve rsion, output power amplifier, and rf filtering. the transmitter path also incorporates ? /4?dqpsk for 2 mbps an d 8?dpsk for 3 mbps to support edr. the transmitter section is compatible to the bluetoot h low energy specification. the transmitter pa bias can also be adjusted to provide bluetooth class 1 or class 2 operation. 4.2.2 digital modulator the digital modulator performs the data modu lation and filtering required for the gfsk, ? /4?dqpsk, and 8?dpsk signal. the fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the trans- mitted signal and is much more stable than direct vco modulation schemes. 4.2.3 digital demodulator and bit synchronizer the digital demodulator and bit synchronizer take the low-if received signal and perform an optimal frequency tracking and bit- synchronization algorithm. 4.2.4 power amplifier the fully integrated pa supports class 1 or class 2 output using a highly linearized, temperature-compensated design. this prov ides greater flexibility in front-end matching and filtering. due to th e linear nature of the pa combi ned with some integrated filte ring, external filtering is required to meet the bluetooth and regulatory harmonic and spurious requirements. for integrated mobile handset ap pli- cations in which bluetooth is integrated next to the cellular radio, external filtering can be applied to achieve near thermal noise levels for spurious and radiated noise emissions. the transmitter featur es a sophisticated on-chip transm it signal strength indicator (tssi) block to keep the absolute output power variation withi n a tight range across process, voltage, and temperature.
document number: 002-14809 rev. *j page 20 of 165 cyw4354 4.2.5 receiver the receiver path uses a low-if scheme to downconvert the rece ived signal for demodulation in the digital demodulator and bit synchronizer. the receiver path provides a high degree of linear ity, an extended dynamic range, and high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 ghz ism band. the front-end topology wi th built-in out-of-band attenuat ion enables the cyw4354 to be used in most applications with minimal off-chip filtering. for integrated handset operation, in which the bluetooth function is integrated close to the cellular transmitter, external filtering is requir ed to eliminate the desensitiza tion of the receiver by the cellular transmit signal. 4.2.6 digital demodulator and bit synchronizer the digital demodulator and bit synchronizer take the low-if received signal and perform an optimal frequency tracking and bit synchronization algorithm. 4.2.7 receiver signal strength indicator the radio portion of the cyw4354 provides a receiver signal streng th indicator (rssi) signal to th e baseband, so that the contr oller can take part in a bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine wheth er the transmitter should increase or decrease its output power. 4.2.8 local oscillator generation local oscillator (lo) generation provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. the lo generation subblock employs an architecture for high immu nity to lo pulling during pa operation. the cyw4354 uses an internal rf and if loop filter. 4.2.9 calibration the cyw4354 radio transceiver features an aut omated calibration scheme that is fully self contained in the radio. no user inter action is required during normal operation or during manufacturing to provide the optimal performance. calibration optimizes the perfo r- mance of all the major blocks within the radio to within 2% of optimal conditions, including gain and phase characteristics of filters, matching between key components, and key gain blocks. this take s into account process variation and temperature variation. calibration occurs transparently during normal operation during t he settling time of the hops and calibrates for temperature va riations as the device cools and heats during normal operation in its environment.
document number: 002-14809 rev. *j page 21 of 165 cyw4354 5. bluetooth baseband core the bluetooth baseband core (bbc) implements all of the time cr itical functions required for hi gh-performance bluetooth operati on. the bbc manages the buffering, segmentation, and routing of dat a for all connections. it also buffers data that passes through it, handles data flow control, schedul es sco/acl tx/rx transactions, monitors blueto oth slot usage, optimal ly segments and packages data into baseband packets, manages connection status indicators , and composes and decodes hci packets. in addition to these functions, it independently handles hci event types, and hci command types. the following transmit and receive functions are also implemented in the bbc hardware to increase reliability and security of t he tx/ rx data before sending over the air: symbol timing recovery, data deframing, forward error correction (fec), header error control (hec), cyclic redundancy check (cr c), data decryption, and data dewhi tening in the receiver. data framing, fec generation, hec generati on, crc generation, key generation, data encryption, and data whitening in the transmitter. 5.1 bluetooth 4.1 features the bbc supports all bluetooth 4.1 fe atures, with the following benefits: dual-mode bluetooth low energy (bt and ble operation) extended inquiry response (eir): shortens the time to re trieve the device name, specif ic profile, and operating mode. encryption pause resume (epr): enables the use of blue tooth technology in a much more secure environment. sniff subrating (ssr): optimizes power consumption for low duty cycle asymmetric data flow, which subsequently extends battery life. secure simple pairing (ssp): reduces the number of steps for connecting two devices, with minima l or no user interaction requir ed. link supervision time out (lsto): additional commands added to hci and link management prot ocol (lmp) for improved link time-out supervision. qos enhancements: changes to data traffic cont rol, which results in better link performa nce. audio, human interface device (hid ), bulk traffic, sco, and enhanced sco (esco) are improved with th e erroneous data (ed) and packet boundary flag (pbf) enhance- ments. 5.2 bluetooth low energy the cyw4354 supports the bluet ooth low energy operating mode. 5.3 link control layer the link control layer is part of the bluetooth link control func tions that are implemented in dedicated logic in the link cont rol unit (lcu). this layer consists of the command contro ller that takes commands from the software, and other controllers that are activated o r configured by the command cont roller, to perform the link cont rol tasks. each task pe rforms a different state in the bluetooth link controller. major states: ? standby ? connection substates: ? page ? page scan ? inquiry ? inquiry scan ? sniff
document number: 002-14809 rev. *j page 22 of 165 cyw4354 5.4 test mode support the cyw4354 fully supports bluetooth test mode as described in part i:1 of the specification of the bluet ooth system version 3.0 . this includes the transmitter tests, normal and del ayed loopback tests, and reduced hopping sequence. in addition to the standard bluetooth test mode, the cyw4354 also supports enhanced testing features to simplify rf debugging a nd qualification and type-approval testing. these features include: fixed frequency carrier wave (unmodulated) transmission ? simplifies some type-approval measurements (japan) ? aids in transmitter performance analysis fixed frequency constant receiver mode ? receiver output directed to i/o pin ? allows for direct ber measurements using standard rf test equipment ? facilitates spurious emissi ons testing for receive mode fixed frequency constant transmission ? eight-bit fixed pattern or prbs-9 ? enables modulated signal measurements with standard rf test equipment 5.5 bluetooth power management unit the bluetooth power management unit (pmu) pr ovides power management features that can be invoked by either software through power management registers or packet handling in the baseband core. the power management func tions provided by the cyw4354 are: rf power management host controller power management bbc power management fm power management 5.5.1 rf power management the bbc generates power-down control signals for the transmit path, receive path, pll, and power amplifier to the 2.4 ghz trans - ceiver. the transceiver then processes the power-down functions accordingly.
document number: 002-14809 rev. *j page 23 of 165 cyw4354 5.5.2 host controller power management when running in uart mode, the cyw4354 may be configured so that dedicated signals are used for power management hand- shaking between the cyw4354 and the host. the basic power saving functions supported by those hand-shaking signals include the standard bluetooth defined power savings modes and standby modes of operation. table 6 describes the power-control hand-shake signals used with the uart interface. note : pad function control register is set to 0 for these pins. see ? dc characteristics? on page 128 for more details table 6. power control pin description signal mapped to pin type description bt_dev_wake bt_gpio_0 i bluetooth device wake-up: sign al from the host to the cyw4354 indicating that the host requires attention. asserted: the bluetooth device must wake-up or remain awake. deasserted: the bluetooth device may sleep when sleep criteria are met. the polarity of this signal is software configurable and can be asserted high or low. bt_host_wake bt_gpio_1 o host wake up. signal from t he cyw4354 to the host indicating that the cyw4354 requires attention. asserted: host device must wake-up or remain awake. deasserted: host device may sleep when sleep criteria are met. the polarity of this signal is software configurable and can be asserted high or low. clk_req bt_clk_req_out wl_clk_req_out o the cyw4354 asserts clk_req when bluetooth or wlan wants the host to turn on the reference clock. the clk_req polarity is active-high. add an external 100 k ? pull-down resistor to ensure the signal is deasserted when the cyw4354 powers up or resets when vddio is present.
document number: 002-14809 rev. *j page 24 of 165 cyw4354 the timing for the startup sequence is defined in figure 6 . figure 6. startup signaling sequence hostresetx vddio lpo bt_gpio_0 (bt_dev_wake ) bt_uart_cts_n clk_req_out bt_gpio_1 (bt_host_wake) bt_reg_on bt_uart_rts_n host i/os configured host i/os unconfigured bth i/os configured bth i/os unconfigured t4 t5 t3 t2 t1 notes: ? t1 is the time for host to settle it?s ios after a reset. ? t2 is the time for host to drive bt_reg_on high after the host ios are configured . ? t3 is the time for bth (bluetooth) device to settle its ios after a reset and reference clock settling time has elapsed . ? t4 is the time for bth device to drive bt_uart_rts_n low after the host drives bt_uart_cts_n low. this assumes the bth device has already completed initialization. ? t5 is the time for bth device to drive clk_req_out high after bt_reg_on goes high. note this pin is used for designs that use a n external reference clock source from the host. this pin is irrelevant for crystal reference clock based designs where the bth device generates it? s own reference clock from an external crystal connected to it?s oscillator circuit. ? timing diagram assumes vbat is present. driven pulled bth device drives this line low indicating transport is ready host side drives this line low
document number: 002-14809 rev. *j page 25 of 165 cyw4354 5.5.3 bbc power management the following are low-power operations for the bbc: physical layer packet-handling turns the rf on and off dynamically within transmit/receive packets. bluetooth-specified low-power connection modes: sniff, hold, and park. while in these modes, t he cyw4354 runs on the low-power oscillator and wakes up after a predefined time period. a low-power shutdown feature a llows the device to be turned off while the host and any other devices in the system remain opera tional. when the cyw4354 is not needed in the system, the rf and core supplies are shut down while the i/o remains powered. this allows the cyw4354 to effectively be off while keeping the i/o pi ns powered so they do not draw extra current fr om any other de vices connected to the i/o. during the low-power shut-down state, provided vddio remains applied to the cyw4354, all outputs are tristated, and most input signals are disabled. inpu t voltages must remain wi thin the limits defined for normal operation. this is done to prevent current paths or create loading on any digital signals in the system and enables the cyw4354 to be fully integrated in an embedded device to take full advantage of the lowest power-saving modes. two cyw4354 input signals are designed to be high-impedance inputs that do not load the driving signal even if the chip does not have vddio power supplied to it: the frequency reference input (wrf_tcxo_in) and the 32.768 khz input (lpo). when the cyw4354 is powered on from this state, it is the same as a normal power-up, and the device does not contain any information about its state from the time before it was powered down. 5.5.4 fm power management the cyw4354 fm subsystem can operate independently of, or in tandem with, the bluetooth rf and bbc subsystems. the fm subsystem power management scheme operates in conjunction with the bluetooth rf and bbc subsystems. the fm block does not have a low power state, it is either on or off. 5.5.5 wideband speech the cyw4354 provides support for wideband speech (wbs) usin g on-chip smartaudio technology. the cyw4354 can perform subband-codec (sbc), as well as msbc, en coding and decoding of linear 16 bits at 16 khz (256 kbps rate) transferred over the pcm bus. 5.5.6 packet loss concealment packet loss concealment (plc) improves apparent audio quality fo r systems with marginal link performance. bluetooth messages are sent in packets. when a packet is lost, it creates a gap in the received audio bit-stream. packet loss can be mitigated in several ways: fill in zeros. ramp down the output audio signal toward zero (thi s is the method used in current bluetoot h headsets). repeat the last frame (or packet) of the received bit-stream and decode it as usual (frame repeat). these techniques cause distortion and popping in the audio stream . the cyw4354 uses a proprietar y waveform extension algorithm to provide dramatic improvem ent in the audio quality. figure 7 and figure 8 show audio waveforms with and without packet loss concealment. broadcom plc/bec algorithms also support wide band speech.
document number: 002-14809 rev. *j page 26 of 165 cyw4354 figure 7. cvsd decoder output waveform without plc figure 8. cvsd decoder output waveform after applying plc 5.5.7 audio rate-matching algorithms the cyw4354 has an enhanced rate-matching algorithm that uses in terpolation algorithms to reduce audio stream jitter that may b e present when the rate of audio data coming from the host is not the same as the bluetooth or fm audio data rates. 5.5.8 codec encoding the cyw4354 can support sbc and msbc encoding and decoding for wideband speech. 5.5.9 multiple simult aneous a2dp audio stream the cyw4354 has the ability to take a single audio stream and ou tput it to multiple bluetooth devices simultaneously. this allo ws a user to share his or her music (or any audio stream) with a friend. 5.5.10 fm over bluetooth fm over bluetooth enables the cyw4354 to st ream data from fm over bluetooth without requiring the host to be awake. this can significantly extend battery life for us age cases where someone is listening to fm radio on a bluetooth headset. 5.5.11 burst buffer operation the cyw4354 has a data buffer that can buffer data being sent over the hci and audio transports, then send the data at an incre ased rate. this mode of operat ion allows the host to sleep for the maximum amo unt of time, dramatically reducing system current consumption. 5.6 adaptive frequency hopping the cyw4354 gathers link quality statistics on a channel by channel basis to faci litate channel assessment and channel map selection. the link quality is determined using both rf and base band signal processing to provide a more accurate frequency-hop map. packet loss causes ramp-down
document number: 002-14809 rev. *j page 27 of 165 cyw4354 5.7 advanced bluetooth/wlan coexistence the cyw4354 includes advanced coexistence technologies that are only possible with a bluetooth/wlan integrated die solution. these coexistence technol ogies are targeted at small form-factor platforms, such as cell pho nes and media play ers, including ap pli- cations such as vowlan + sco and video-over-wlan + high fidelity bt stereo. support is provided for platforms that share a single antenna between bluetooth and wlan. dual-antenna applications are also supported. the cyw4354 radio architecture allows for lossless simultaneous bluetoot h and wlan reception for shared antenna applications. this is possible only via an integrated solution (shared lna and joint agc algorithm). it has superior performanc e versus implementations that need to arbitrate between bluetooth and wlan reception. the cyw4354 integrated solution enables mac-layer signaling (fi rmware) and a greater degree of sharing via an enhanced coexis- tence interface. information is exchanged between the blue tooth and wlan cores without host processor involvement. the cyw4354 also supports transmit power control on the sta toge ther with standard bluetooth tpc to limit mutual interference and receiver desensitization. pr eemption mechanisms are utilized to prevent ap transmissions from colliding with bluetooth fram es. improved channel classification techniques have been implemented in bluetooth for faster and more accurate detection and elimi- nation of interferers (including non-wlan 2.4 ghz interference). the bluetooth afh classification is also enhanced by the wlan core?s channel information. 5.8 fast connection (interlaced page and inquiry scans) the cyw4354 supports page scan and inquiry scan modes that si gnificantly reduce the average inquiry response and connection times. these scanning modes are compatible with the bluetooth version 2.1 page and inquiry procedures.
document number: 002-14809 rev. *j page 28 of 165 cyw4354 6. microprocessor and memory unit for bluetooth the bluetooth microprocessor core is based on the arm ? cortex-m3? 32-bit risc proce ssor with embedded ice-rt debug and jtag interface units. it runs software from the link cont rol (lc) layer, up to the host controller interface (hci). the arm core is paired with a memory unit that contains 668 kb of rom memory for program stor age and boot rom, 200 kb of ram for data scratchpad and patch ram code. the internal rom a llows for flexibility during power-on reset to enable the same de vice to be used in various configurations. at power-up, the lower-lay er protocol stack is executed from the internal rom memory. external patches may be applied to the rom-based firmware to pr ovide flexibility for bug fixes or features additions. these pat ches may be downloaded from the host to the cyw4354 through the uart transports. the mechanism for downloading via uart is identical to the proven interface of the cyw4330 device. 6.1 ram, rom, and patch memory the cyw4354 bluetooth core has 200 kb of internal ram which is mapped between general purpose scratch pad memory and patch memory and 668 kb of rom used for the lower-layer protocol stack, test mode software, and boot rom. the patch memory capability enables the addition of code changes for purposes of feature additions and bug fixes to the rom memory. 6.2 reset the cyw4354 has an integrated power-on reset circuit that resets all circuits to a known power-on state. the bt power-on reset (por) circuit is out of reset after bt_reg_on goes high. if bt_reg_on is low, then the por circuit is held in reset.
document number: 002-14809 rev. *j page 29 of 165 cyw4354 7. bluetooth periph eral transport unit 7.1 spi interface the cyw4354 supports a slave spi hci transport with an input cl ock range of up to 16 mhz. higher clock rates can be possible. t he physical interface between the spi master and the cyw4354 consists of the four spi signals (spi_csb, spi_clk, spi_si, and spi_so) and one interrupt signal (spi_int). the spi signals are muxed onto the uart signals, see table 7 . the cyw4354 can be configured to accept active-low or active-high polarity on t he spi_csb chip select signal. it can also be configured to drive a n active- low or active-high spi_int interrupt signal. bit ordering on th e spi_si and spi_so data lines can be configured as either littl e-endian or big-endian. additionally, proprietary sleep mode and half-dupl ex handshaking is implemented between the spi master and the cyw4354. the spi_int is required to negotiate the start of a transaction. the spi interface does not require flow control in th e middle of a payload. the fifo is large enough to ha ndle the largest packet size. only the spi master can stop the flow of bytes on the data lines, since it controls spi_csb and spi_clk. flow cont rol should be implemented in the higher layer protocols. 7.2 spi/uart transport detection the bt_host_wake (bt_gpio1) pin is also used for bt transpor t detection. the transport dete ction occurs during the power-up sequence. it selects either uart or spi tr ansport operation based on the following pin state: if the bt_host_wake (bt_gpio1) pin is pulled low by an external pull-down during power- up, it selects the spi transport interfa ce. if the bt_host_wake (bt_gpio1) pin is not pulled low externally during power-up, then the def ault internal pull-up is detected as a high and it selects the uart transport interface. 7.3 pcm interface the cyw4354 supports two independent pcm in terfaces that share the pins with the i 2 s interfaces. the pcm interface on the cyw4354 can connect to linear pcm codec devices in master or slave mode. in master mode, the cyw4354 generates the pcm_clk and pcm_sync signals, and in slave mode, these signal s are provided by another master on the pcm interface and are inputs to the cyw4354. the configuration of the pcm interface may be adjusted by the host through the use of vendor-specific hci commands. 7.3.1 slot mapping the cyw4354 supports up to three simultaneous full-duplex sc o or esco channels through the pcm interface. these three channels are time-multiplexed onto the single pcm interface by us ing a time-slotting scheme where the 8 khz or 16 khz audio sam ple interval is divided into as many as 16 slots. the number of slots is dependent on the selected in terface rate of 128 khz, 512 k hz, or 1024 khz. the corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. transmit and receive pcm data from an sco channel is always mapped to the same slot. t he pcm data output driver tristate s its output on unused slots to allow other devices to share the same pcm interface signals. the data output driver tristates its ou tput after the falling edge of th e pcm clock during the last bit of the slot. 7.3.2 frame synchronization the cyw4354 supports both short- and long-frame synchronization in both master and slave modes. in short-frame synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. the pcm slave looks for a high on the falling edge of the bit clock and expec ts the first bit of the first slot to start at th e next rising edge of the cl ock. in long-frame synchroni zation mode, the frame synchr onization signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts c oincident with the first bit of the first slot. table 7. spi to uart signal mapping spi signals uart signals spi_clk uart_cts_n spi_csb uart_rts_n spi_miso uart_txd spi_mosi uart_rxd spi_int bt_dev_wake
document number: 002-14809 rev. *j page 30 of 165 cyw4354 7.3.3 data formatting the cyw4354 may be configured to generate and accept several di fferent data formats. for conventional narrowband speech mode, the cyw4354 uses 13 of the 16 bits in each pcm frame. the lo cation and order of these 13 bits can be configured to support vari ous data formats on the pcm interface. the remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. the default format is 13-bit 2? s complement data, left justified, and clocked msb first. 7.3.4 wideband speech support when the host encodes wideband speech (wbs) packets in transpa rent mode, the encoded packets are transferred over the pcm bus for an esco voice connection. in this mode, the pcm bus is ty pically configured in master m ode for a 4 khz sync rate with 1 6- bit samples, resulting in a 64 kbps bit rate. the cyw4354 also supports slave transparent mode using a proprietary rate-matchin g scheme. in sbc-code mode, linear 16-bit data at 16 kh z (256 kbps rate) is transferred over the pcm bus. 7.3.5 multiplexed bluetooth and fm over pcm in this mode of operation, the cyw4354 multiplexes both fm a nd bluetooth audio pcm channels over the same interface, reducing the number of required i/os. this mode of operation is initiate d through an hci command from the host. the format of the data s tream consists of three channels: a bluetooth channel followed by two fm channels (audio left and right). in this mode of operation, the bus data rate only supports 48 khz operation per channel with 16 bits sent for each channel. this is done to allow the low data rat e bluetooth data to coexist in the sa me interface as the higher speed i 2 s data. to accomplish this, the bluetooth data is repeated six times for 8 khz data and three times for 16 khz data. an initial sync pulse on the pcm_sync line is used to indicate the beginn ing of the frame. to support multiple bluetooth audio stream s within the bluetooth channel, both 16 khz and 8 khz streams can be multiplexed. thi s mode of operation is only supported when the bluetooth ho st is the master. figure 9 shows the operation of the multiplexed transport with three simultaneous sco connections. to accommodate additi onal sco channels, the transport clock speed is increased. to change between modes of operation, the transport must be halted and restarted in the new configuration. figure 9. functional multiplex data diagram 7.3.6 burst pcm mode in this mode of operation, the pcm bus runs at a significantly higher rate of operati on to allow the host to duty cycle its ope ration and save current. in this mode of operation, the pcm bus can operate at a rate of up to 24 mhz. this mode of operation is initiated with an hci command from the host. pcm_sync pcm_in pcm_out fm ? right fm ? left fm ? right fm ? left bt ? sco ? 1 ? tx bt ? sco ? 2 ? tx bt ? sco ? 3 ? tx bt ? sco ? 1 ? rx bt ? sco ? 2 ? rx bt ? sco ? 3 ? rx 1 ? frame pcm_clk 16 ? bits ? per ? sco ? frame ? clk 16 ? bits ? per ? frame ? 16 ? bits ? per ? frame ? each ? sco ? channel ? duplicates ? the ? data ? 6 ? times. ?? each ? wbs ? frame ? duplicates ? the ? data ? three ? times ? per ? frame
document number: 002-14809 rev. *j page 31 of 165 cyw4354 7.3.7 pcm interface timing short frame sync, master mode figure 10. pcm timing diagram (short frame sync, master mode) table 8. pcm interface timing specifications (short frame sync, master mode) ref no. characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 pcm_sync delay 0 ? 25 ns 5 pcm_out delay 0 ? 25 ns 6 pcm_in setup 8 ? ? ns 7 pcm_in hold 8 ? ? ns 8 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 0 ? 25 ns pcm_bclk pcm_sync pcm_out 1 23 4 5 pcm_in 6 8 high ? impedance 7
document number: 002-14809 rev. *j page 32 of 165 cyw4354 short frame sync, slave mode figure 11. pcm timing diagram (short frame sync, slave mode) table 9. pcm interface timing specifications (short frame sync, slave mode) ref no. characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 pcm_sync setup 8 ? ? ns 5 pcm_sync hold 8 ? ? ns 6 pcm_out delay 0 ? 25 ns 7 pcm_in setup 8 ? ? ns 8 pcm_in hold 8 ? ? ns 9 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 0?25ns pcm_bclk pcm_sync pcm_out 1 23 4 5 6 pcm_in 7 9 high ? impedance 8
document number: 002-14809 rev. *j page 33 of 165 cyw4354 long frame sync, master mode figure 12. pcm timing diagram (long frame sync, master mode) table 10. pcm interface timing specificat ions (long frame sync, master mode) ref no. characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 pcm_sync delay 0 ? 25 ns 5 pcm_out delay 0 ? 25 ns 6pcm_in setup 8 ?? ns 7 pcm_in hold 8 ? ? ns 8 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 0?25ns pcm_bclk pcm_sync pcm_out 1 23 4 5 pcm_in 8 high ? impedance bit ? 0 bit ? 0 bit ? 1 bit ? 1 6 7
document number: 002-14809 rev. *j page 34 of 165 cyw4354 long frame sync, slave mode figure 13. pcm timing diagram (long frame sync, slave mode) table 11. pcm interface timing specifications (long frame sync, slave mode) ref no. characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 pcm_sync setup 8 ? ? ns 5 pcm_sync hold 8 ? ? ns 6 pcm_out delay 0 ? 25 ns 7 pcm_in setup 8 ? ? ns 8 pcm_in hold 8 ? ? ns 9 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 0?25ns pcm_bclk pcm_sync pcm_out 1 23 4 5 6 pcm_in 7 9 high ? impedance 8 bit ? 0 bit ? 0 bit ? 1 bit ? 1
document number: 002-14809 rev. *j page 35 of 165 cyw4354 short frame sync, burst mode figure 14. pcm burst mode timing (receive only, short frame sync) table 12. pcm burst mode (receive only, short frame sync) ref no. characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 24 mhz 2 pcm bit clock low 20.8 ? ? ns 3 pcm bit clock high 20.8 ? ? ns 4 pcm_sync setup 8 ? ? ns 5 pcm_sync hold 8 ? ? ns 6 pcm_in setup 8 ? ? ns 7 pcm_in hold 8 ? ? ns pcm_bclk pcm_sync 1 23 45 pcm_in 6 7
document number: 002-14809 rev. *j page 36 of 165 cyw4354 long frame sync, burst mode figure 15. pcm burst mode timing (receive only, long frame sync) table 13. pcm burst mode (receive only, long frame sync) ref no. characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 24 mhz 2 pcm bit clock low 20.8 ? ? ns 3 pcm bit clock high 20.8 ? ? ns 4pcm_sync setup 8 ?? ns 5 pcm_sync hold 8 ? ? ns 6pcm_in setup 8 ?? ns 7 pcm_in hold 8 ? ? ns pcm_bclk pcm_sync 1 2 3 4 5 pcm_in 6 7 bit ? 0 bit ? 1
document number: 002-14809 rev. *j page 37 of 165 cyw4354 7.4 usb interface 7.4.1 features the following usb interface features are supported: usb protocol, revision 2.0, full-speed (12 mbps) compliant including the hub optional hub compound device with up to three device cores internal to device bus or self-power, dynamic configuration for the hub global and selective suspend and resume with remote wake-up bluetooth hci hid, dfu, uhe (proprietary method to emulate an hi d device at system bootup) integrated detach resistor 7.4.2 operation the cyw4354 can be configured to boot up as either a single usb peripheral or a usb hub with several usb peripherals attached. as a single peripheral, the host detects a single usb bluetooth dev ice. in hub mode, the host detects a hub with one to three o f the ports already connected to usb devices (see figure 16 ). figure 16. usb compounded device configuration depending on the desired hub mode configuration, the cyw4354 ca n boot up showing the three ports connected to logical usb devices internal to the cyw4354: a generic bluetooth device, a mous e, and a keyboard. in this mode, the mouse and keyboard are emulated devices, since they connect to real hid devices via a bl uetooth link. the bluetooth link to these hid devices is hidde n from the usb host. to the host, the mouse and/or keyboard appear to be directly connected to the usb po rt. this broadcom proprietary architecture is called usb hid emulation (uhe). the usb device, configuration, and string descriptors are fully programmable, allowing manufacturers to customize the descripto rs, including vendor and product ids, the cyw4354 uses to identify itself on the usb por t. to make custom u sb descriptor informatio n available at boot time, stor ed it in external nvram. despite the mode of operation (single peripher al or hub), the bluetooth device is conf igured to include the following interface s: interface 0 contains a control endpoint (endpoint 0x00) for hci commands, a bulk in endpoint (endpoint 0x82) for receiving acl data, a bulk out endpoint (endpoint 0x02) for transm itting acl data, and an interrupt endpoint (endpoint 0x81) for hci events. interface 1 contains isochronous in and out endpoints (endpoints 0x83 and 0x03) for sco traffic. several alternate interface 1 settings are available for reserving the proper bandw idth of isochronous data (depending on the application). interface 2 contains bulk in and bulk out endpoints (endpoint s 0x84 and 0x04) used for proprietary testing and debugging purposes. these endpoints can be ignored during normal operation. usb ? compounded ? device hub ? controller usb ? device ? 1 hid ? keyboard ? usb ? device ? 2 hid ? mouse usb ? device ? 3 bluetooth host
document number: 002-14809 rev. *j page 38 of 165 cyw4354 7.4.3 usb hub and uhe support the cyw4354 supports the usb hub and device model (usb, revisi on 2.0, full-speed compliant). optional mouse and keyboard devices utilize broadcom?s proprietary usb hid emulation (uhe) ar chitecture, which allows these devices appear as standalone hi d devices even though connecte d through a bluetooth link. the presence of uhe devices requires the hub to be enabled. the cy w4354 cannot appear as a single keyboard or a single mouse device without the hub. once either mouse or keyboard uhe device is enabled, the hub must also be enabled. when the hub is enabled, the cyw4354 handles al l standard usb functions for the following devices: hid keyboard hid mouse bluetooth all hub and device descriptors are firmware-programm able. this usb compound device configuration (see figure 16 on page 37 ) supports up to three downstream ports. this configuration can also be programmed to a single usb device core. the device automa t- ically detects activity on the usb interfac e when connected. therefore, no special configuration is needed to select hci as the transport. the hub?s downstream port definition is as follows: port 1 usb lite device core (for hid applications) port 2 usb lite device core (for hid applications) port 3 usb full device core (for bluetooth applications) when operating in hub mode, all three internal devices do not ha ve to be enabled. each internal usb device can be optionally en abled. the configuration record in nvram de termines which devices are present. 7.4.4 usb full-speed timing ta b l e 1 4 shows timing specifications for the vdd_usb = 3.3v, v ss = 0v, and t a = 0c to 85c operating temperature range. figure 17. usb full-speed timing table 14. usb full-speed timing specifications reference characteristics minimum maximum unit 1 transition rise time 4 20 ns 2 transition fall time 4 20 ns 3 rise/fall timing matching 90 111 % 4 full-speed data rate 12 ? 0.25% 12 + 0.25% mb/s d+ d- v crs 90% 90% 10% 10% 1 2
document number: 002-14809 rev. *j page 39 of 165 cyw4354 7.5 uart interface the cyw4354 shares a single uart for bluetooth and fm. the uart is a standard 4-wire interface (rx, tx, rts, and cts) with adjustable baud rates from 9600 bps to 4.1 mbps. the interface features an automatic baud rate detection capability that return s a baud rate selection. alternatively, the baud rate may be selected through a vendor-specific uart hci command. uart has a 1040-byte receive fifo and a 1040-byte transmit fifo to support edr. access to the fifos is conducted through the ahb interface through either dma or the cpu. the uart supports the bluetooth 4.1 uart hci specification: h4, a custom extended h4, and h5. the default baud rate is 115.2 kbaud. the uart supports the 3-wire h5 uart transport, as described in the bluetooth specific ation (?three-wire uart transport layer?) . compared to h4, the h5 uart transport reduces the number of signal lines required by eliminating the cts and rts signals. the cyw4354 uart can perform xon/xoff flow control and includes hardware support fo r the serial line input protocol (slip). it can also perform wake-on activi ty. for example, activity on the rx or cts inputs can wake the chip from a sleep state. normally, the uart baud rate is set by a configuration record downloaded after device reset, or by automatic baud rate detectio n, and the host does not need to adjust the baud rate. support for changing the baud rate during normal hci uart operation is incl uded through a vendor-specific command that allo ws the host to adjust the contents of t he baud rate registers. the cyw4354 uarts operate correctly with the host uart as long as the co mbined baud rate error of the two devices is within 2%. table 15. example of common baud rates desired rate actual rate error (%) 4000000 4000000 0.00 3692000 3692308 0.01 3000000 3000000 0.00 2000000 2000000 0.00 1500000 1500000 0.00 1444444 1454544 0.70 921600 923077 0.16 460800 461538 0.16 230400 230796 0.17 115200 115385 0.16 57600 57692 0.16 38400 38400 0.00 28800 28846 0.16 19200 19200 0.00 14400 14423 0.16 9600 9600 0.00
document number: 002-14809 rev. *j page 40 of 165 cyw4354 figure 18. uart timing table 16. uart timi ng specifications ref no. characteristics minimum typical maximum unit 1 delay time, uart_cts_n low to uart_txd valid ? ? 1.5 bit periods 2 setup time, uart_cts_n high before midpoint of stop bit ? ? 0.5 bit periods 3 delay time, midpoint of stop bit to uart_rts_n high ? ? 0.5 bit periods uart_cts_n uart_rxd uart_rts_n 1 2 midpoint ? of ? stop ? bit uart_txd midpoint ? of ? stop ? bit 3
document number: 002-14809 rev. *j page 41 of 165 cyw4354 7.6 i 2 s interface the cyw4354 supports two independent i 2 s digital audio ports: one for bluetooth audio, and one for high-fidelity fm audio. the i 2 s interface for fm audio supports both master and slave modes. the i 2 s signals are: i 2 s clock: bt_i2s_clk i 2 s word select: bt_i2s_ws i 2 s data out: bt_i2s_do i 2 s data in: bt_i2s_di bt_i2s_clk and bt_i2s_ws become outputs in master mode and inputs in slave mode, whereas bt_i2s_do always stays as an output. the channel word length is 16 bits, and the data is just ified so that the msb of the le ft-channel data is aligned with the msb of the i 2 s bus, in accord with the i 2 s specification. the msb of each data word is transmitted one bit clock cycle af ter the bt_i2s_ws transition, synchronous with the falling edge of the bit clock. left-channel data is transmitted when ibt_i2s_ws is low, and ri ght- channel data is transmitted when bt_i2s_ws is high. data bits sent by the cyw4354 are synchronized with the falling edge of bt_i2s_clk and should be sampled by the re ceiver on the rising edge of bt_i2s_clk. the clock rate in master mode is either of the following: 48 khz x 32 bits per frame = 1.536 mhz 48 khz x 50 bits per frame = 2.400 mhz the master clock is generated from the inpu t reference clock using a n/m clock divider. in the slave mode, any clock rate is supported to a maximum of 3.072 mhz.
document number: 002-14809 rev. *j page 42 of 165 cyw4354 7.6.1 i 2 s timing note : timing values specified in table 16 are relative to high and low threshold levels note: the time periods specified in figure 19 and figure 20 are defined by the transmitter speed. the receiver specifications must match transmitter performance. table 17. timing for i 2 s transmitters and receivers transmitter receiver notes lower limit upper limit lower limit upper limit min. max. min. max. min. max. min. max. clock period t t tr ???t r ??? a a. the system clock period t must be greater than t tr and t r because both the transmitter and receiver ha ve to be able to handle the data transfer rate. master mode: clock generated by transmitter or receiver high t hc 0.35t tr ???0.35t tr ??? b b. at all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. for thi s reason, t hc and t lc are specified with respect to t. lowt lc 0.35t tr ???0.35t tr ??? b slave mode: clock accepted by transmitter or receiver high t hc ?0.35t tr ? ? ? 0.35t tr ?? c c. in slave mode, the transmitter and receiver need a clock signal with minimum high and low periods so that they can detect the signal. so long as the minimum periods are greater than 0.35t r , any clock that meets the requirements can be used. low t lc ?0.35t tr ? ? ? 0.35t tr ?? c rise time t rc ? ? 0.15t tr ????? d d. because the delay (t dtr ) and the maximum transmitter speed (defined by t tr ) are related, a fast transmitter driven by a slow clock edge can result in t dtr not exceeding t rc which means t htr becomes zero or negative. therefore, the transmitter has to guarantee that t htr is greater than or equal to zero, so long as the clock rise-time t rc is not more than t rcmax , where t rcmax is not less than 0.15t tr . transmitter delay t dtr ???0.8t???? e e. to allow data to be clocked out on a fall ing edge, the delay is specified with res pect to the rising edge of the clock signal and t, always giving the receiver sufficient setup time. hold time t htr 0??????? d receiver setup time t sr ?????0.2t r ?? f f. the data setup and hold time must not be less than the specified receiver setup and hold time. hold time t hr ?????0?? f
document number: 002-14809 rev. *j page 43 of 165 cyw4354 figure 19. i 2 s transmitter timing figure 20. i 2 s receiver timing sd ? and ? ws sck v l = ? 0.8v t lc > 0.35t t rc * t hc > 0.35t t v h = ? 2.0v t htr > 0 t otr < 0.8t t ? = ? clock ? period t tr = ? minimum ? allowed ? clock ? period ? for ? transmitter t ? = ? t tr * ? t rc is ? only ? relevant ? for ? transmitters ? in ? slave ? mode. sd ? and ? ws sck v l = ? 0.8v t lc > 0.35t t hc > 0.35 t v h = ? 2.0v t hr > 0 t sr > 0.2t t ? = ? clock ? period t r = ? minimum ? allowed ? clock ? period ? for ? transmitter t ? > ? t r
document number: 002-14809 rev. *j page 44 of 165 cyw4354 8. fm recei ver subsystem 8.1 fm radio the cyw4354 includes a completely integrated fm radio receiver with rds/rbds covering all fm bands from 65 mhz to 108 mhz. the receiver is controlled through commands on the hci. fm received audio is available as stereo or in digital form through i 2 s or pcm. the fm radio operates from the external clock reference. 8.2 digital fm audio interfaces the fm audio can be transmitted via the shared pcm and i 2 s pins, and the sampling rate is programmable. the cyw4354 supports a three-wire pcm or i 2 s audio interface in either master or slave configuration. the master or slave configuration is selected using vendor specific commands over the hci interf ace. in addition, multiple sampling rates are supported, derived from either the fm or bluetooth clocks. in master mode, the clock rate is either of the following: 48 khz 32 bits per frame = 1.536 mhz 48 khz 50 bits per frame = 2.400 mhz in slave mode, any clock rate is supported up to a maximum of 3.072 mhz. 8.3 fm over bluetooth the cyw4354 can output received fm audio onto bluetooth using one of following thr ee links: esco, wbs, and a2dp. in all of the above modes, once the link has been set up, the host processor can enter sleep mode while the cyw4 354 continues to stream fm audio to the remote bluetooth device, allowing the system current consumption to be minimized. 8.4 esco in this use case, the stereo fm audio is downsampled to 8 khz and a mono or stereo stream is th en sent through the bluetooth es co link to a remote bluetooth device, typically a headset. two bluetooth voice connections must be used to transport stereo. 8.5 wide band speech link in this case, the stereo fm audio is downsampled to 16 khz and a mono or stereo stream is then sent through the bluetooth wideb and speech link to a remote bluetooth device, typically a headset. tw o bluetooth voice connections must be used to transport stereo . 8.6 a2dp in this case, the stereo fm audio is enco ded by the on-chip sbc encoder and transport ed as an a2dp link to a remote bluetooth device. sampling rates of 48 khz, 44.1 khz, and 32 khz joint ster eo are supported. an a2dp ?lite? stack is implemented in the cyw4354 to support this use case, which eliminates the need to route the sbc-encoded audio back to the host to create the a2dp packets. 8.7 autotune and search algorithms the cyw4354 supports a number of fm search and tune functions that allows the host to implement many conven ient user functions, which are accessed through the broadcom fm stack. tune to play: allows the fm receiver to be programmed to a specific frequency. search for snr > threshold: checks the power level of the ava ilable channel and the estimated s nr of the channel to help achiev e precise control of the expected sound qualit y for the selected fm channel. specifica lly, the host can adjust its snr requiremen ts to retrieve a signal with a specific sound quality, or adjust this to return the weakest channels. alternate frequency jump: allows the fm receiver to automaticall y jump to an alternate fm channel that carries the same informa tion, but has a better snr. for exampl e, when traveling, a user may pass through a regi on where a number of channels carry the same station. when the user passes from one area to the next, the fm receiver can automatically swit ch to another channel with a str onger signal to spare the user from having to manually change the channel to continue listening to the same station.
document number: 002-14809 rev. *j page 45 of 165 cyw4354 8.8 audio features a number of features are implemented in the cyw4354 to pr ovide the best possible audio experience for the user. mono/stereo blend or switch: the cyw4354 provides automatic contro l of the stereo or mono sett ings based on the fm signal carrier-to-noise ratio (c/n). this feature is used to maintain the best possible audio snr based on the fm channel condition. t wo modes of operation are supported: ? blend: in this mode, fine control of ster eo separation is used to ac hieve optimal audio quality ov er a wide range of input c/n. the amount of separation is fully programmable. in figure 21 , the separation is programmed to maintain a minimum 50 db snr across the blend range. ? extended blend: in this mode, stereo se paration is maximized across a wide range of input cnr. broadcom static suppression typically gives a static-free user experienc e to within 3 db of ultimate sensitivity. figure 21. example blend/switch usage ? switch: in this mode, the audio switches fr om full stereo to full mono at a predeterm ined level to maintain optimal audio quali ty. the stereo-to-mono switch point and the mo no-to-stereo switch points are fully progra mmable to provide the desired amount of audio snr. in figure 22 , the switch point is programmed to sw itch to mono to maintain a 40 db snr.
document number: 002-14809 rev. *j page 46 of 165 cyw4354 figure 22. example blend/switch separation soft mute: improves the user experience by dynamically muting the output audio proporti onate to the fm signal c/n. this prevent s the user from being assaulted with a blast of static. the mute characteristic is full y programmable to accommodate fine tuning of the output signal level. an example mute characteristic is shown in figure 23 . figure 23. example soft mute characteristic
document number: 002-14809 rev. *j page 47 of 165 cyw4354 high cut: a programmable high-cut filter is provided to reduce t he amount of high-frequency noise caused by static in the outpu t audio signal. like the soft mute circuit, it is fully programmable to allow for any amount of high cut based on the fm signal c /n. audio pause detect: the fm receiver monitors the magnitude of the audio signal and notifies the host through an interrupt when the magnitude of the signal has fallen below the threshold set for a programmable period. this feature can be used to provide alternate frequency jumps during periods of silence to minimize disturbances to the listener. fi ltering techniques are used wit hin the audio pause detection block to provide more robust presenc e-to-silence detection and silence-to-presence detection. automatic antenna tuning: the cyw4354 has an on-chip automati c antenna tuning network. when used with a single off-chip inductor, the on-chip circuitry automatically chooses an optimal on-chip matching component to obtain the highest signal streng th for the desired frequency. the high-q nature of this matching network simultaneously pr ovides out-of-band blocking protection a s well as a reduction of radiated spurious emissions from the fm antenna. it is designed to accommodate a wide range of external wire antennas. 8.9 rds/rbds the cyw4354 integrates a rds/rbds modem and codec, the decoder includes programmable filtering and buffering functions, and the encoder includes the option to encode messages to ps or rt frame format with programmable scrolling in ps mode. the rds/ rbds data can be read out in receive mode or delivered in transmit mode through either the hci interface. in addition, the rds/rbds functi onality supports the following: receive block decoding, error correction and synchronization flywheel synchronization feature, allowing the host to set paramete rs for acquisition, maintenanc e, and loss of sync. (it is po ssible to set up the cyw4354 such that synch is achieved when a mini mum of two good blocks (error free) are decoded in sequence. the number of good blocks required for sync is programmable.) storage capability up to 126 blocks of rds data full or partial block b match detect and interrupt to host audio pause detection with programmable parameters program identification (pi) code detection and interrupt to host automatic frequency jump block e filtering soft mute signal dependent mono/stereo blend programmable pre-emphasis
document number: 002-14809 rev. *j page 48 of 165 cyw4354 9. wlan global functions 9.1 wlan cpu and memory subsystem the cyw4354 wlan section includes an integrated arm cortex-r 4? 32-bit processor with internal ram and rom. the arm cortex-r4 is a low-power processor that features low gate coun t, low interrupt latency, and low-cost debug capabilities. it is intended for deeply embedded applications that require fast interrupt resp onse features. delivering a perfo rmance gain of more than 30% over the arm7tdmi? processor, the arm cortex-r4 processor implem ents the arm v7-r architecture with support for the thumb ? -2 instruction set. at 0.19 w/mhz, the cortex-r4 is the most power efficient general-purpose microproce ssor available, outperforming 8- and 16-bit devices on mips/w. using multiple technologies to reduce cost, the arm cortex-r4 of fers improved memory utilization, reduced pin overhead, and reduced silicon area. it supports independent buses for code an d data access (icode/dcode and system buses), integrated sleep modes, and extensive debug features including real time trace of program execution. on-chip memory for the cpu includes 768 kb sram and 640 kb rom. 9.2 one-time programmable memory various hardware configuration parameters may be stored in an in ternal one-time programmable (otp) memory, which is read by the system software after device reset. in addition, cu stomer-specific pa rameters, including the system vendor id and the mac address can be stored, depending on the spec ific board design. up to 484 bytes of user-accessible otp are available. the initial state of all bits in an unprogra mmed otp device is 0. after any bit is pr ogrammed to a 1, it cannot be reprogrammed to 0. the entire otp array can be program med in a single write cycle using a utility provided with the broadcom wlan manufacturing te st tools. alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits which are still in the 0 state can be altered during each programming cycle. prior to otp programming, all values should be verified using th e appropriate editable nvram.txt file, which is provided with t he reference board design package. 9.3 gpio interface the cyw4354 has 11 general-purpose i/o (gpio) pins in the wlan section that can be used to connect to various external devices. upon power-up and reset, these pins become tr istated. subsequently, they can be programmed to be either input or output pins vi a the gpio control register. in addit ion, the gpio pins can be assigned to various other functions, see table 27 on page 97 .
document number: 002-14809 rev. *j page 49 of 165 cyw4354 9.4 external coexistence interface an external handshake interface is available to enable signalin g between the device and an external co-located wireless device, such as gps, or lte, to manage wireless me dium sharing for optimal performance. figure 24 and figure 25 on page 49 show the lte coexistence interface (inclu ding uart) for each cyw4354 package type. see table 27 on page 97 for further details on multiplexed signals, such as the gpio pins. see table 16 on page 40 for the uart baud rate. figure 24. cypress gci mode lte coexistence interface figure 25. legacy 3-wire lte coexistence interface wlan gci lte/ic uart_in uart_out btfm notes: ? ? or?ing ? to ? generate ? ism_rx_priority ? for ? ercx_txconf ? or ? bt_rx_priority ? is ? achieved ? by ? setting ? the ? gpio ? mask ? registers ? appropriately. ? seci_out ? and ? seci_in ? are ? multiplexed ? on ? the ? gpios. seci_out seci_in cyw4354 note: ? or?ing ? to ? generate ? wcn_priority ? for ? ercx_txconf ? or ? bt_rx_priority ? is ? achieved ? by ? setting ? the ? gpio ? mask ? registers ? appropriately. wlan gci lte/ic bt/fm wcn_priority gci_gpio_2 gci_gpio_1 gci_gpio_0 mws_rx, ? lte_priority lte_frame_sync cyw4354
document number: 002-14809 rev. *j page 50 of 165 cyw4354 9.5 uart interface one 2-wire uart interface can be enabled by softwa re as an alternate functi on on gpio pins. refer to table 27 on page 97 . provided primarily for debugging during development, this uart enables the cyw4354 to operate as rs-2 32 data termination equipment (dte) for exchanging and managing data with other serial device s. it is compatible with the industry standard 16550 uart, and provides a fifo size of 64 8 in each direction. 9.6 jtag interface the cyw4354 supports the ieee 1149.1 jtag boundary scan stan dard for performing device packa ge and pcb assembly testing during manufacturing. in addition, the jtag interface allows br oadcom to assist customers by using proprietary debug and charac - terization test tools during board bring-up. therefore, it is highly recommended to prov ide access to the jtag pins by means of test points or a header on all pcb designs. refer to table 27 on page 97 for jtag pin assignments. 9.7 sprom interface various hardware configuration parameters may be stored in an external sprom instead of the otp. the sprom is read by system software after de vice reset. in addition, depending on the board design, customer-specific parameters may be stored in sprom. the four sprom control signals ?sprom_cs, sprom_clk, sprom_m i, and sprom_mo are multiplexed on the sdio interface (see table 27 on page 97 for additional details). by default, the sprom interf ace supports 2 kbit serial sproms, and it can also support 4 kbit and 16 kbit serial sproms by using the appropriate strapping option. 9.8 sflash interface for use only when the hsic interface mode is selected, an interface to external sflash is available. the four sflash control signals ?sflash_cs#, sflash_clk , sflash_mi, and sflash_mo are multiplexed on the sdio interface (see table 27 on page 97 for additional details).
document number: 002-14809 rev. *j page 51 of 165 cyw4354 10. wlan ho st interfaces 10.1 sdio v3.0 all three package options of the cyw4354 wlan section provide support for sdio version 3.0, including the new uhs-i modes: ds: default speed (ds) up to 25 mhz, including 1- and 4-bit modes (3.3v signaling). hs: high-speed up to 50 mhz (3.3v signaling). sdr12: sdr up to 25 mhz (1.8v signaling). sdr25: sdr up to 50 mhz (1.8v signaling). sdr50: sdr up to 100 mhz (1.8v signaling). sdr104: sdr up to 208 mhz (1.8v signaling) ddr50: ddr up to 50 mhz (1.8v signaling). note : the cyw4354 is backward compatible with sdio v2.0 host interfaces. the sdio interface also has the ability to map the interrupt signal on to a gpio pin for applications requiring an interrupt di fferent from the one provided by the sdio interface. the ability to force control of the gated clocks from within the device is also pr ovided. sdio mode is enabled by strapping options. refer to table 24 on page 96 wlan gpio functions and strapping options. the following three functions are supported: function 0 standard sdio function (max. blocksize/bytecount = 32b) function 1 backplane function to access the internal system -on-chip (soc) address space (max. blocksize/bytecount = 64b) function 2 wlan function for efficient wlan packet transfer through dma (max. blocksize/bytecount = 512b) 10.1.1 sdio pins table 18. sdio pin descriptions sd 4-bit mode sd 1-bit mode data0 data line 0 data data line data1 data line 1 or interrupt irq interrupt data2 data line 2 or read wait rw read wait data3 data line 3 n/c not used clk clock clk clock cmd command line cmd command line
document number: 002-14809 rev. *j page 52 of 165 cyw4354 figure 26. signal connections to sdio host (sd 4-bit mode) figure 27. signal connections to sdio host (sd 1-bit mode) note: per section 6 of the sdio spec ification, pull-ups in the 10 k ? to 100 k ? range are required on the four data lines and the cmd line. this requirement must be met during all ope rating states either through the use of external pull-up resistors or through proper programming of the sdio host?s internal pull-ups. sd ? host clk cmd dat[3:0] cyw4354 sd ? host clk cmd data irq rw cyw4354
document number: 002-14809 rev. *j page 53 of 165 cyw4354 10.2 hsic interface as an alternative to sdio, an hsic host interface can be enabled using the strapping option pins strap_host_ifc_[3:1]. hsic is a simplified derivative of the usb2.0 interfac e designed to replace a standard usb phy and cable for short distances (up to 10 cm) on board point-to-point connections. using two signals, a bidirectional data strobe (strobe) and a bidirectional ddr data signal ( data), it provides high-speed serial 480 mbps data transfers that are 1 00% host driver compatible with traditional usb 2.0 cable-conne cted topologies. figure 28 shows the blocks in the hsic device core. key features of hsic include: high-speed 480 mbps data rate source-synchronous serial interface using 1.2v lvcmos signal levels no power consumed except when a data transfer is in progress maximum trace length of 10 cm. no plug-n-play support, no hot attach/removal figure 28. hsic de vice block diagram 10.3 pci express interface the pci express (pcie?) core on the cyw4354 is a high-performanc e serial i/o interconnect that is protocol compliant and electr i- cally compatib le with the pci express base specification v3.0 running at gen1 speeds. this core contains all the necessary blocks, including logical and electrical functional subblocks to perfor m pcie functionality and maintain high-speed links, using existi ng pci system configuratio n software implementation s without modification. organization of the pcie core is in logi cal layers: transaction layer, data link layer, and physical layer, as shown in figure 29 . a configuration or link management block is provided for enumerating the pcie config uration space and supporting generation and reception of system manag ement messages by commun icating with pcie layers. each layer is partitioned into dedicated transmit and receive units that allow point-to-point communication between the host an d cyw4354 device. the transmit side processes outbound packets w hereas the receive side processe s inbound packets. packets are formed and generated in the transaction and data link layer for transmission onto the high-speed links and onto the receiving d evice. a header is added at the beginning to indicate the packet type and any other optional fields. 32 \ bit ? on \ chip ? communication ? system dma ? engines rx ? fifo tx ? fifos tx ? fifos tx ? fifos tx ? fifos tx ? fifos tx ? fifos endpoint ? management ? unit usb ? 2.0 ? protocol ? engine hsic ? phy strobe data
document number: 002-14809 rev. *j page 54 of 165 cyw4354 figure 29. pci express layer model 10.3.1 transaction layer interface the pcie core employs a packet-based protocol to transfer data between the host and cyw4354 device, delivering new levels of performance and features. the upper layer of the pcie is the tr ansaction layer. the transaction layer is primarily responsible for assembly and disassembly of transaction layer packets (tlps). tlp structure contains header, data payload, and end-to-end crc (ecrc) fields, which are used to communicate transactio ns, such as read and write requests and other events. a pipelined full split-transaction protocol is implemented in this layer to maximize efficient communication between devices wi th credit- based flow control of tlp, which eliminates wasted link bandwidth due to retries. 10.3.2 data link layer the data link layer serves as an intermediate stage between the transaction layer and the physical layer. its primary responsib ility is to provide reliable, efficient mechanism for the exchange of tlps between two directly connected components on the link. servic es provided by the data link layer include data exchange, initia lization, error detection and correction, and retry services. data link layer packets (dllps) are generated and consumed by th e data link layer. dllps are the mechanism used to transfer lin k management information between data link laye rs of the two directly connected compo nents on the link, including tlp acknowl- edgement, power management, and flow control. 10.3.3 physical layer the physical layer of the pcie provides a handshake mechanism between the data link layer and the high-speed signaling used for link data interchange. th is layer is divided into the logi cal and electrical functional subb locks. both subblocks have dedicate d transmit and receive units that allow for point-to-point communication be tween the host and cyw4354 device. the transmit section prepare s outgoing information passed from the data link layer for transmi ssion, and the receiver section identifies and prepares receive d information before passing it to the data link layer. this proc ess involves link initialization, configuration, scrambler, and data conversion into a specific format. 10.3.4 logical subblock the logical sub block primary functions are to prepare outgoing data from the data link layer for transmission and identify rec eived data before passing it to the data link layer. 10.3.5 scramb ler/descrambler this pcie phy component generates pseudo-ra ndom sequence for scrambling of data byte s and the idle sequence. on the transmit side, scrambling is applied to characters prior to the 8b/10b enc oding. on the receive side, descrambling is applied to charact ers after 8b/10b decoding. scrambling may be disabled in polling and recovery for testing and debugging purposes. transaction layer data ? link layer logical ? subblock electrical ? subblock physical ? layer transaction layer data ? link layer logical ? subblock electrical ? subblock physical ? layer hw/sw ? interface hw/sw ? interface tx rx tx rx
document number: 002-14809 rev. *j page 55 of 165 cyw4354 10.3.6 8b/10b encoder/decoder the pcie core on the cyw4354 uses an 8b/10b encoder/decoder sc heme to provide dc balancing, synchronizing clock and data recovery, and error detection. the transmission code is specified in the ansi x3.230-1994, clause 11 and in ieee 802.3z, 36.2.4 . using this scheme, 8-bit data characters are treated as 3 bits and 5 bits mapped onto a 4-bit code group and a 6-bit code group , respectively. the control bit in conjunction with the data characte r is used to identify when to encode one of the twelve speci al symbols included in the 8b/10b transmission code. these code groups are co ncatenated to form a 10-bit symbol, which is then transmitted serially. special symbols are used for link management, frame tlps, and dllps, allowing these packets to be quickly identified and easily distinguished. 10.3.7 elastic fifo an elastic fifo is implemented in the receiver side to compens ate for the differences between the transmit clock domain and the receive clock domain, with worse case clock frequency specified at 600 ppm tolerance. as a result, the transmit and receive clo cks can shift one clock every 1666 clo cks. in addition, the fi fo adaptively ad justs the elastic level bas ed on the rela tive frequen cy difference of the write and read clock. this technique reduces the elastic fifo size and the average receiver latency by half. 10.3.8 electrical subblock the high-speed signals utilize the common mode logic (cml) signal ing interface with on-chip termination and de-emphasis for bes t- in-class signal integrity. a de-emphasis technique is employed to reduce the effects of intersymbo l interference (isi) due to t he interconnect by optimizing voltage and timing margins for worst case channel loss. this results in a maximally open ?eye? at th e detection point, thereby allowing the receiver to rece ive data with acceptable bit-error rate (ber). to further minimize isi, multiple bits of the same polarity that are output in succession are de-emphasized. subsequent same bi ts are reduced by a factor of 3.5 db in power. th is amount is specified by pcie to allow for maximum interoperability while minimizing the complexity of controlling the de-emphasis values. the high-speed interface requires ac coupling on the transmit side to elimina te the dc common mode voltage from the receiver. the range of ac capacitance allowed is 75 nf to 200 nf. 10.3.9 configuration space the pcie function in the cyw4354 implements the configuration space as defined in the pci express base specification v3.0 .
document number: 002-14809 rev. *j page 56 of 165 cyw4354 11. wireless lan mac and phy 11.1 ieee 802.11ac draft mac the cyw4354 wlan mac is designed to support high-throughput operat ion with low-power consumption. it does so without compro- mising the bluetooth coexistence policies, thereby enabling optima l performance over both networks. in addition, several power saving modes have been implemented that allow the mac to consume very little power while maintaining network-wide timing synchroni- zation. the architecture diagram of the mac is shown in figure 30 . the following sections provide an overview of the important modules in the mac. figure 30. wlan mac architecture embedded ? cpu ? interface host ? registers, ? dma ? engines tx \ fifo 32 ? kb wep tkip, ? aes, ? wapi txe tx ? a \ mpdu rxe pmq psm shared ? memory 6 ? kb psm ucode memory ext \ ihr ifs backoff, ? btcx tsf nav ihr ? bus shm ? bus mac \ phy ? interface rx \ fifo 10 ? kb rx ? a \ mpdu
document number: 002-14809 rev. *j page 57 of 165 cyw4354 the cyw4354 wlan media access controller (mac) supports feat ures specified in the ieee 802.11 base standard, and amended by ieee 802.11n. the key mac features include: enhanced mac for supporting ieee 802.11ac draft features transmission and reception of aggregated mpdus (a-mpdu) for high throughput (ht) support for power management schemes, including wmm power -save, power-save multi-poll (psmp) and multiphase psmp operation support for immediate ack and block-ack policies interframe space timing support, including rifs support for rts/cts and cts-to-self fram e sequences for protecting frame exchanges back-off counters in hardware for supporting multiple priorities as specified in the wmm specification timing synchronization function (tsf), network allocation vector (nav) maintenance, and target beacon transmission time (tbtt) generation in hardware hardware offload for aes-ccmp, legacy wpa tkip, legacy wep ciphers, wapi, and support for key management support for coexistence with bluetooth and other external radios programmable independent basic service set (ibss) or infrastructure basic service set functionality statistics counters for mib support 11.1.1 psm the programmable state machine (psm) is a mi cro-coded engine, which provides most of the low-level control to the hardware, to implement the ieee 802.11 sp ecification. it is a microcontroll er that is highl y optimized for flow control operations, which ar e predom- inant in implementations of communication protocols. the inst ruction set and fundamental operations are simple and general, whi ch allows algorithms to be optimized until very late in the design process. it also allows for changes to the algorithms to track evolving ieee 802.11 specifications. the psm fetches instructions from the microc ode memory. it uses the shared memory to obtain operands for instructions, as a dat a store, and to exchange data bet ween both the host and the mac data pipeline (via the shm bus). the psm also uses a scratchpad memory (similar to a register bank) to stor e frequently accessed and temporary variables. the psm exercises fine-grained control over the hardware engines, by programming internal hardw are registers (i hr). these ihrs are co-located with the hardw are functions they control, and are a ccessed by the psm via the ihr bus. the psm fetches instructions from the micr ocode memory using an address determined by the program counter, instruction literal, or a program stack. for alu operations t he operands are obtained from shared memory, scratchpad, ihrs, or instruction literals, and the results are written into the s hared memory, scratchpad, or ihrs. there are two basic branch instructions: cond itional branches and alu based branches. to better support the many decision point s in the ieee 802.11 algorithms, branches c an depend on either a readily available signals from the hardware modules (branch cond ition signals are available to the psm without polling the ihrs), or on the results of alu operations. 11.1.2 wep the wired equivalent privacy (wep) engine encapsulates all the ha rdware accelerators to perform the encryption and decryption, and mic computation and verification. the accelerators implement th e following cipher al gorithms: legacy wep, wpa tkip, wpa2 aes- ccmp. the psm determines, based on the frame type and association info rmation, the appropriate cipher algorithm to be used. it suppli es the keys to the hardware engines from an on-chip key table. the wep interfaces with the txe to encrypt and compute the mic on transmit frames, and the rxe to decrypt and verify the mic on receive frames.
document number: 002-14809 rev. *j page 58 of 165 cyw4354 11.1.3 txe the transmit engine (txe) constitutes the transmit data path of the mac. it coordinates the dma engines to store the transmit f rames in the txfifo. it interfaces with wep module to encrypt frames , and transfers the frames acro ss the mac-phy interface at the appropriate time determined by the channel access mechanisms. the data received from the dma engines are stored in transmit fi fos. the mac supports multiple logical queues to support traffi c streams that have different qos priority requirements. the psm uses the channel access information from the ifs module to sched ule a queue from which the next frame is transmitted. once the fram e is scheduled, the txe hardware transmits the frame based on a precise timing trigger received from the ifs module. the txe module also contains the hardware t hat allows the rapid assembly of mpdus in to an a-mpdu for tr ansmission. the hardware module aggregates the encrypted mpdus by adding appropriate headers and pad delimiters as needed. 11.1.4 rxe the receive engine (rxe) constitutes the receive data path of t he mac. it interfaces with the dma engine to drain the received frames from the rxfifo. it transfers bytes across the mac-phy interfac e and interfaces with the wep m odule to decrypt frames. the decrypted data is stored in the rxfifo. the rxe module contains programmable filters that are programmed by the psm to accept or filter frames based on several criteri a such as receiver address, b ssid, and certain frame types. the rxe module also contains the hardware required to detect a-mpdus, parse the headers of t he containers, and disaggregate them into component mpdus. 11.1.5 ifs the ifs module contains the timers required to determine interf rame space timing including rifs timing. it also contains multip le backoff engines required to support prioritized access to the medium as specified by wmm. the interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the phy. these timers provide precise timing to the txe to begin frame transmission. th e txe uses this information to send response frames or perform transmit frame-bursting (rifs or sifs separated, as within a txop). the backoff engines (for each access category) monitor channel ac tivity, in each slot duration, to determine whether to continu e or pause the backoff counters. when the backoff counters reach 0, t he txe gets notified, so that it may commence frame transmissio n. in the event of multiple backoff counters decrementing to 0 at the same time, the hardware resolves the conflict based on polic ies provided by the psm. the ifs module also incorporates hardware that allows the mac to enter a low-power state when operating under the ieee power save mode. in this mode, the mac is in a suspended state with its clock turned off. a sleep time r, whose count value is initial ized by the psm, runs on a slow clock and determines the duration over which the mac remains in this suspended state. once the timer expires the mac is restored to its functi onal state. the psm updates the tsf timer based on the sleep duration ensuring that th e tsf is synchronized to the network. the ifs module also contains the pta hardware that assists the psm in bluetooth coexistence functions. 11.1.6 tsf the timing synchronization function (tsf) module maintains the tsf timer of the mac. it also ma intains the target beacon trans- mission time (tbtt). the tsf timer hardware, under the control of the psm, is capable of adopting timestamps received from beac on and probe response frames in order to ma intain synchronization with the network. the tsf module also generates trigger signals fo r events that are specified as offsets from the tsf timer, such as uplink and d ownlink transmission times used in psmp. 11.1.7 nav the network allocation vector (nav) timer module is responsible for maintaining the nav information conveyed through the durati on field of mac frames. this ensures that the mac complies with the protection me chanisms specified in the standard. the hardware, under the control of the psm, maintains the nav ti mer and updates the timer appropriately based on received frame s. this timing information is provided to the ifs module, which uses it as a virtual carrier-sense indication. 11.1.8 mac-phy interface the mac-phy interface consists of a data path interface to e xchange rx/tx data from/to the phy. in addition, there is an programming interface, which can be controlled either by the host or the psm to configure and control the phy.
document number: 002-14809 rev. *j page 59 of 165 cyw4354 11.2 ieee 802.11ac draft phy the cyw4354 wlan digital phy (see figure 31 on page 60 ) is designed to comp ly with ieee 802.11ac draft and ieee 802.11a/b/g/n dual-stream specifications to provide wirele ss lan connectivity supporting data rates from 1 mbps to 866.7 mbps for low-power, high-performance handheld applications. the phy has been designed to work in the presence of inte rference, radio nonlinearity, and various other impairments. it incorporates optimized implementations of the filters, fft and viterbi decoder algorithms. efficient algorithms have been designed to achieve maximum thr oughput and reliability, including algor ithms for carrier sense/rejection, frequency/phase/timing acquisition and tracking, channel esti mation and tracking. the phy receiver also contains a robust ieee 802.11b demodulator. the ph y carrier sense has been t uned to provide high th roughput for ieee 802.11g/ 11b hybrid networks with bluetooth coex istence. it has also been designed for sharing an antenna between wl and bt to support simultaneous rx-rx. the key phy features include: programmable data rates from mcs0?15 in 20 mhz, 40 mhz, and 80 mhz channels, as specified in ieee 802.11ac draft supports optional short gi and green field modes in tx and rx tx and rx ldpc for improved range and power efficiency beamforming support all scrambling, encoding, forward error correction, and modulati on in the transmit direction and inverse operations in the rece ive direction. supports ieee 802.11h/k for worldwide operation advanced algorithms for low power, enhanced sensitivity, range, and reliability algorithms to improve perform ance in presence of bluetooth closed loop transmit power control digital rf chip calibration algorithms to handle cmos rf chip non-idealities on-the-fly channel frequency and transmit power selection supports per packet rx antenna diversity available per-packet channel quality and signal strength measurements designed to meet fcc and other worldwide regulatory requirements
document number: 002-14809 rev. *j page 60 of 165 cyw4354 figure 31. wlan phy block diagram filters ? and ? radio ? comp frequency ? and ? timing ? synch carrier ? sense, ? agc, ? and ? rx ? fsm radio ? control ? block common ? logic ? block filters ? and ? radio ? comp afe ? and ? radio mac ? interface buffers ofdm ? demodulate viterbi ? decoder tx ? fsm pa ? comp modulation ? and ? coding modulate/ spread frame ? and ? scramble fft/ifft cck/dsss ? demodulate descramble ? and ? deframe coex
document number: 002-14809 rev. *j page 61 of 165 cyw4354 12. wlan radio subsystem the cyw4354 includes an integrated dual-band wlan rf transceiver that has been optimized for us e in 2.4 ghz and 5 ghz wireless lan systems. it has been designed to provide low-power, low-cost , and robust communications for applications op erating in the globally available 2.4 ghz unlicensed ism or 5 ghz u-nii bands. the transmit and receive sections include all on-chip filtering , mixing, and gain control functions. sixteen rf control signals are available (eight per core) to driv e external rf switches and suppo rt optional external power amp lifiers and low-noise amplifiers for each band. see t he reference board schemat ics for further details. a block diagram of the radio subsystem (core 0) is shown in figure 32 on page 62 . core 1, is identical to core 0 without the bluetooth blocks. the integrated on-chip baluns (not shown) conver t the fully differential transmit an d receive paths to single-ended sig nal pins. 12.1 receiver path the cyw4354 has a wide dynamic range, direct conversion receiv er that employs high order on-chip channel filtering to ensure reliable operation in the noisy 2.4 ghz ism band or the entire 5 ghz u-nii band. an on-chip low noise amplifier (lna) in the 2. 4 ghz path in core 0 is shared between the bluetooth and wlan receiver s, whereas the 5 ghz receive path and the core 1 2.4 ghz receiv e path have dedicated on-chip lnas. control signals are available that can support the use of external lnas for each band, which can increase the receive sensitivity by several db. 12.2 transmit path baseband data is modulated and upconverted to the 2.4 ghz ism or 5 ghz u-nii bands, respectively. linear on-chip power amplifier s are included, which are capable of delivering high output powe r while meeting ieee 802.11ac and ieee 802.11a/b/g/n specificatio ns, and without the need for external pas. when using the internal pa s, closed-loop output power c ontrol is completely integrated.
document number: 002-14809 rev. *j page 62 of 165 cyw4354 figure 32. radio functional block diagram (core 0) 12.3 calibration the cyw4354 features dynamic and automatic on-chip calibration to continually compensa te for temperature and process variations across components. these calibration routines are performed period ically in the course of normal radio operation. examples of s ome of the automatic calibration algorithms are baseband filter calibration for optimum tran smit and receive performance, and loft calibration for carrier leakage reduction. in addition, i/q ca libration, r calibration, and vco calibration are performed on-ch ip. no per-board calibration is required in manufacturi ng test, which helps to minimize the test time and cost in large volume product ion. gm bt ? logen wl ? logen bt ? pll wl ? pll wlan ? bb bt ? bb clb voltage ? regulators bt ? fm lpo/ext ? lpo/rcal wl ? adc bt ? adc bt ? dac wl ? pa wl ? pad wl ? pga wl ? tx ? g \ mixer wl ? dac wl ? a \ pa wl ? a \ pad wl ? a \ pga wl ? tx ? a \ mixer wl ? txlpf wl ? rxlpf wl ? rx ? a \ mixer wl ? rx ? g \ mixer wl ? a \ lna11 wl ? a \ lna12 slna wl ? g \ lna12 bt ? lna ? load bt ? lna ? gm bt ? pa bt ? rx ? mixer bt ? tx ? mixer bt ? rxlpf bt ? txlpf shared ? xo wl ? txlpf wl ? dac wl ? adc wl ? rxlpf wl ? atx wl ? grx wl ? gtx wl ? arx mux bt ? tx bt ? rx bt ? adc bt ? rxlpf bt ? dac
document number: 002-14809 rev. *j page 63 of 165 cyw4354 13. pinout and signal descriptions 13.1 ball maps figure 33 and figure 34 on page 64 show the wlbga ball map. figure 33. wlbga ball map, 4.87 mm 7.67 mm arra y, 192-ball, a1?v6 (bottom view?balls facing up) 65 4 3 2 1 hsic_data pcie_refclkn pcie_refclkp pcie_tdn pcie_tdp a hsic_agnd12pll pcie_pll_avss pcie_rxtx_avss pcie_pll _avdd1p2 pcie_rxtx _avdd1p2 pcie_rdn b hsic_dvdd12 pcie_pme_l pcie_perst_l pcie_testp pcie_testn pcie_rdp c vssc pcie_clkreq_l vddc vssc d gpio_9 bt_usb_dn bt_vddc fm_audiovdd1p2 fm_aout1 e lpo_in bt_usb_dp clk_req fm_pllvdd1p2 fm_audiovss fm_aout2 f bt_i2s_do bt_i2s_di vssc fm_pllvss fm_vcovss fm_lnavcovdd1p2 g bt_uart_rxd bt_pcm_out bt_vddc fm_lnavss fm_rfin h bt_i2s_clk bt_uart_txd bt_pcm_in bt_host_wake bt_vcovss bt_vcovdd1p2 j bt_pcm_sync bt_uart_rts_l bt_gpio_4 bt_ifvdd1p2 bt_pllvdd1p2 bt_lnavdd1p2 k bt_i2s_ws bt_uart_cts_l bt_dev_wake bt_pllvss bt_pavss bt_rf l bt_pcm_clk bt_vddc vssc bt_ifvss bt_pavdd2p5 m rf_sw_ctrl_4 wrf_rx2g _gnd1p2_core0 wrf_lna_2g _gnd1p2_core0 wrf_rfin _2g_core0 n rf_sw_ctrl_6 wrf_afe _gnd1p2_core0 wrf_tx _gnd1p2_core0 wrf_pa2g_vbat _gnd3p3_core0 wrf_rfout _2g_core0 p wrf_logen _gnd1p2 wrf_logeng _gnd1p2 wrf_gpio _out_core0 wrf_padrv_vbat _vdd3p3_core0 wrf_pa2g_vbat _gnd3p3_core0 wrf_pa2g_vbat _vdd3p3_core0 r wrf_mmd _gnd1p2 wrf_mmd _vdd1p2 wrf_pfd _vdd1p2 wrf_padrv_vbat _gnd3p3_core0 wrf_pa5g_vbat _gnd3p3_core0 wrf_pa5g_vbat _vdd3p3_core0 t wrf_vco _gnd1p2 wrf_pfd _gnd1p2 wrf_buck _vdd1p5 core0 wrf_tssi_a _core0 wrf_pa5g_vbat _gnd3p3_core0 wrf_rfout _5g_core0 u wrf_synth _vbat_vdd3p3 wrf_cp _gnd1p2 wrf_buck _gnd1p5_core0 wrf_rx5g _gnd1p2_core0 wrf_lna_5g _gnd1p2_core0 wrf_rfin _5g_core0 v 65 4 3 2 1
document number: 002-14809 rev. *j page 64 of 165 cyw4354 figure 34. wlbga ball map, 4.87 7.67 array, 192-ball, a7 ? v12 (bottom view?balls facing up) 12 11 10 9 8 7 a sr _pvss sr _vlx wl_reg_on sdio_cmd sdio_clk hsic_strobe b sr _vddbatp5v sr _vddbata5v pmu_avss sdio_data_0 sdio_data_2 vddc c ldo _vdd1p5 vout _cldo vssc sdio_data_1 sdio_data_3 hsic_avdd12pll d vout _btldo2p5 vout _lnldo bt_reg_on jtag_sel rrefhsic e ldo _vddbat5v vout _ldo3p3_b vddio vddc vddio_sd gpio_7 f vout _3p3 gpio_2 gpio_1 gpio_5 gpio_6 gpio_8 g vssc gpio_0 vddc gpio_3 vssc avss_bbpll h gpio_10 vddio_rf gpio_4 avdd_bbpll jvddc rf_sw _ctrl_9 rf_sw_ctrl_12 vddc k rf_sw _ctrl_8 rf_sw _ctrl_13 bt_vddio l vssc vddc rf_sw_ctrl_11 rf_sw_ctrl_15 vssc m rf_sw _ctrl_10 rf_sw _ctrl_14 rf_sw_ctrl_7 vddc n wrf_xtal _out wrf_xtal _gnd1p2 wrf_xtal _vdd1p2 rf_sw_ctrl_1 rf_sw_ctrl_3 p wrf_xtal _in wrf_xtal _vdd1p5 rf_sw_ctrl_2 rf_sw_ctrl_5 r wrf_buck _gnd1p5_core1 wrf_buck _vdd1p5_core1 wrf_gpio_out _core1 wrf_afe _gnd1p2_core1 rf_sw_ctrl_0 t wrf_rx5g _gnd1p2_core1 wrf_tssi _a_core1 wrf_padrv_vbat _gnd3p3_core1 wrf_padrv_vbat _vdd3p3_core1 wrf_tx _gnd1p2_core1 wrf_rx2g _gnd1p2_core1 u wrf_lna _5g_gnd1p2_core1 wrf_pa5g_vbat _gnd3p3_core1 wrf_pa5g_vbat _gnd3p3_core1 wrf_pa2g_vbat _gnd3p3_core1 wrf_pa2g_vbat _gnd3p3_core1 wrf_lna_2g _gnd1p2_core1 v wrf_rfin _5g_core1 wrf_rfout _5g_core1 wrf_pa5g_vbat _vdd3p3_core1 wrf_pa2g_vbat _vdd3p3_core1 wrf_rfout _2g_core1 wrf_rfin _2g_core1 12 11 10 9 8 7
document number: 002-14809 rev. *j page 65 of 165 cyw4354 13.2 pin lists table 19. pin list by pin number (192-pin wlbga package) wlbga ball# pin name a10 wl_reg_on a11 sr_vlx a12 sr_pvss a2 pcie_tdp0 a3 pcie_tdn0 a4 pcie_refclkp a5 pcie_refclkn a6 hsic_data a7 hsic_strobe a8 sdio_clk a9 sdio_cmd b1 pcie_rdn0 b10 pmu_avss b11 sr_vddbata5v b12 sr_vddbatp5v b2 pcie_rxtx_avdd1p2 b3 pcie_pll_avdd1p2 b4 pcie_rxtx_avss b5 pcie_pll_avss b6 hsic_agnd12pll b7 vdd/vddc b8 sdio_data_2 b9 sdio_data_0 c1 pcie_rdp0 c10 vssc/vss c11 vout_cldo c12 ldo_vdd1p5 c2 pcie_testn c3 pcie_testp c4 pcie_perst_l c5 pcie_pme_l c6 hsic_dvdd12 c7 hsic_avdd12pll c8 sdio_data_3 c9 sdio_data_1 d10 bt_reg_on d11 vout_lnldo d12 vout_btldo2p5 d3 vssc/vss d4 vdd/vddc d5 pcie_clkreq_l d6 vssc/vss d7 rrefhsic d9 jtag_sel e1 fm_aout1 e10 vddio e11 vout_ldo3p3_b e12 ldo_vddbat5v e2 fm_audiovdd1p2 e4 bt_vdd/vddc e5 bt_usb_dn e6 gpio_9 e7 gpio_7 e8 vddio_sd e9 vdd/vddc f1 fm_aout2 f10 gpio_1 f11 gpio_2 f12 vout_3p3 f2 fm_audiovss f3 fm_pllvdd1p2 f4 clk_req f5 bt_usb_dp f6 lpo_in f7 gpio_8 f8 gpio_6 f9 gpio_5 g1 fm_lnavcovdd1p2 g10 vdd/vddc g11 gpio_0 g12 vssc/vss g2 fm_vcovss g3 fm_pllvss g4 vssc/vss g5 bt_i2s_di g6 bt_i2s_do g7 avss_bbpll g8 vssc/vss g9 gpio_3 h1 fm_rfin h11 vddio_rf h12 gpio_10 wlbga ball# pin name
document number: 002-14809 rev. *j page 66 of 165 cyw4354 h2 fm_lnavss h3 bt_vdd/vddc h4 bt_pcm_out h5 bt_uart_rxd h7 avdd_bbpll h9 gpio_4 j1 bt_vcovdd1p2 j11 rf_sw_ctrl_9 j12 vdd/vddc j2 bt_vcovss j3 bt_host_wake j4 bt_pcm_in j5 bt_uart_txd j6 bt_i2s_clk j8 vdd/vddc j9 rf_sw_ctrl_12 k1 bt_lnavdd1p2 k10 rf_sw_ctrl_13 k12 rf_sw_ctrl_8 k2 bt_pllvdd1p2 k3 bt_ifvdd1p2 k4 bt_gpio_4 k5 bt_uart_rts_l k6 bt_pcm_sync k7 bt_vddio l1 bt_rf l10 vdd/vddc l11 vssc/vss l2 bt_pavss l3 bt_pllvss l4 bt_dev_wake l5 bt_uart_cts_l l6 bt_i2s_ws l7 vssc/vss l8 rf_sw_ctrl_15 l9 rf_sw_ctrl_11 m1 bt_pavdd2p5 m10 rf_sw_ctrl_14 m12 rf_sw_ctrl_10 m3 bt_ifvss m4 vssc/vss m5 bt_vdd/vddc m6 bt_pcm_clk wlbga ball# pin name m7 vdd/vddc m8 rf_sw_ctrl_7 n1 wrf_rfin_2g_core0 n10 wrf_xtal_vdd1p2 n11 wrf_xtal_gnd1p2 n12 wrf_xtal_out n2 wrf_lna_2g_gnd1p2_core0 n3 wrf_rx2g_gnd1p2_core0 n5 rf_sw_ctrl_4 n7 rf_sw_ctrl_3 n8 rf_sw_ctrl_1 p1 wrf_rfout_2g_core0 p11 wrf_xtal_vdd1p5 p12 wrf_xtal_in p2 wrf_pa2g_vbat_gnd3p3_core0 p3 wrf_tx_gnd1p2_core0 p4 wrf_afe_gnd1p2_core0 p5 rf_sw_ctrl_6 p7 rf_sw_ctrl_5 p9 rf_sw_ctrl_2 r1 wrf_pa2g_vbat_vdd3p3_core0 r11 wrf_buck_vdd1p5_core1 r12 wrf_buck_gnd1p5_core1 r2 wrf_pa2g_vbat_gnd3p3_core0 r3 wrf_padrv_vbat_vdd3p3_core0 r4 wrf_gpio_out_core0 r5 wrf_logeng_gnd1p2 r6 wrf_logen_gnd1p2 r7 rf_sw_ctrl_0 r8 wrf_afe_gnd1p2_core1 r9 wrf_gpio_out_core1 t1 wrf_pa5g_vbat_vdd3p3_core0 t10 wrf_padrv_vbat_gnd3p3_core1 t11 wrf_tssi_a_core1 t12 wrf_rx5g_gnd1p2_core1 t2 wrf_pa5g_vbat_gnd3p3_core0 t3 wrf_padrv_vbat_gnd3p3_core0 t4 wrf_pfd_vdd1p2 t5 wrf_mmd_vdd1p2 t6 wrf_mmd_gnd1p2 t7 wrf_rx2g_gnd1p2_core1 t8 wrf_tx_gnd1p2_core1 t9 wrf_padrv_vbat_vdd3p3_core1 wlbga ball# pin name
document number: 002-14809 rev. *j page 67 of 165 cyw4354 u1 wrf_rfout_5g_core0 u10 wrf_pa5g_vbat_gnd3p3_core1 u11 wrf_pa5g_vbat_gnd3p3_core1 u12 wrf_lna_5g_gnd1p2_core1 u2 wrf_pa5g_vbat_gnd3p3_core0 u3 wrf_tssi_a_core0 u4 wrf_buck_vdd1p5_core0 u5 wrf_pfd_gnd1p2 u6 wrf_vco_gnd1p2 u7 wrf_lna_2g_gnd1p2_core1 u8 wrf_pa2g_vbat_gnd3p3_core1 u9 wrf_pa2g_vbat_gnd3p3_core1 v1 wrf_rfin_5g_core0 v10 wrf_pa5g_vbat_vdd3p3_core1 v11 wrf_rfout_5g_core1 v12 wrf_rfin_5g_core1 v2 wrf_lna_5g_gnd1p2_core0 v3 wrf_rx5g_gnd1p2_core0 v4 wrf_buck_gnd1p5_core0 v5 wrf_cp_gnd1p2 v6 wrf_synth_vbat_vdd3p3 v7 wrf_rfin_2g_core1 v8 wrf_rfout_2g_core1 v9 wrf_pa2g_vbat_vdd3p3_core1 wlbga ball# pin name
document number: 002-14809 rev. *j page 68 of 165 cyw4354 table 20. pin list by pin name (192-pin wlbga package) pin name wlbga ball# avdd_bbpll h7 avss_bbpll g7 bt_dev_wake l4 bt_gpio_4 k4 bt_host_wake j3 bt_i2s_clk j6 bt_i2s_di g5 bt_i2s_do g6 bt_i2s_ws l6 bt_ifvdd1p2 k3 bt_ifvss m3 bt_lnavdd1p2 k1 bt_pavdd2p5 m1 bt_pavss l2 bt_pcm_clk m6 bt_pcm_in j4 bt_pcm_out h4 bt_pcm_sync k6 bt_pllvdd1p2 k2 bt_pllvss l3 bt_reg_on d10 bt_rf l1 bt_uart_cts_l l5 bt_uart_rts_l k5 bt_uart_rxd h5 bt_uart_txd j5 bt_usb_dn e5 bt_usb_dp f5 bt_vcovdd1p2 j1 bt_vcovss j2 bt_vddio k7 clk_req f4 fm_aout1 e1 fm_aout2 f1 fm_audiovdd1p2 e2 fm_audiovss f2 fm_lnavcovdd1p2 g1 fm_lnavss h2 fm_pllvdd1p2 f3 fm_pllvss g3 fm_rfin h1 fm_vcovss g2 gpio_0 g11 gpio_1 f10 gpio_10 h12 gpio_2 f11 gpio_3 g9 gpio_4 h9 gpio_5 f9 gpio_6 f8 gpio_7 e7 gpio_8 f7 gpio_9 e6 hsic_agnd12pll b6 hsic_avdd12pll c7 hsic_data a6 hsic_dvdd12 c6 hsic_strobe a7 jtag_sel d9 ldo_vdd1p5 c12 ldo_vddbat5v e12 lpo_in f6 pcie_pme_l c5 pcie_clkreq_l d5 pcie_perst_l c4 pcie_pll_avdd1p2 b3 pcie_pll_avss b5 pcie_rdn0 b1 pcie_rdp0 c1 pcie_refclkn a5 pcie_refclkp a4 pcie_rxtx_avdd1p2 b2 pcie_rxtx_avss b4 pcie_tdn0 a3 pcie_tdp0 a2 pcie_testn c2 pcie_testp c3 pmu_avss b10 rf_sw_ctrl_0 r7 rf_sw_ctrl_1 n8 rf_sw_ctrl_10 m12 rf_sw_ctrl_11 l9 rf_sw_ctrl_12 j9 rf_sw_ctrl_13 k10 rf_sw_ctrl_14 m10 rf_sw_ctrl_15 l8 pin name wlbga ball#
document number: 002-14809 rev. *j page 69 of 165 cyw4354 rf_sw_ctrl_2 p9 rf_sw_ctrl_3 n7 rf_sw_ctrl_4 n5 rf_sw_ctrl_5 p7 rf_sw_ctrl_6 p5 rf_sw_ctrl_7 m8 rf_sw_ctrl_8 k12 rf_sw_ctrl_9 j11 rrefhsic d7 sdio_clk a8 sdio_cmd a9 sdio_data_0 b9 sdio_data_1 c9 sdio_data_2 b8 sdio_data_3 c8 sr_pvss a12 sr_vddbata5v b11 sr_vddbatp5v b12 sr_vlx a11 vdd/vddc b7 vdd/vddc d4 bt_vdd/vddc e4 vdd/vddc e9 vdd/vddc g10 bt_vdd/vddc h3 vdd/vddc j12 vdd/vddc j8 vdd/vddc l10 bt_vdd/vddc m5 vdd/vddc m7 vddio e10 vddio_rf h11 vddio_sd e8 vout_3p3 f12 vout_btldo2p5 d12 vout_cldo c11 vout_ldo3p3_b e11 vout_lnldo d11 vssc/vss c10 vssc/vss d3 vssc/vss d6 vssc/vss g12 vssc/vss g4 vssc/vss g8 pin name wlbga ball# vssc/vss l11 vssc/vss l7 vssc/vss m4 wl_reg_on a10 wrf_afe_gnd1p2_core0 p4 wrf_afe_gnd1p2_core1 r8 wrf_buck_gnd1p5_core0 v4 wrf_buck_gnd1p5_core1 r12 wrf_buck_vdd1p5_core0 u4 wrf_buck_vdd1p5_core1 r11 wrf_cp_gnd1p2 v5 wrf_gpio_out_core0 r4 wrf_gpio_out_core1 r9 wrf_lna_2g_gnd1p2_core0 n2 wrf_lna_2g_gnd1p2_core1 u7 wrf_lna_5g_gnd1p2_core0 v2 wrf_lna_5g_gnd1p2_core1 u12 wrf_logen_gnd1p2 r6 wrf_logeng_gnd1p2 r5 wrf_mmd_gnd1p2 t6 wrf_mmd_vdd1p2 t5 wrf_pa2g_vbat_gnd3p3_core0 p2 wrf_pa2g_vbat_gnd3p3_core0 r2 wrf_pa2g_vbat_gnd3p3_core1 u8 wrf_pa2g_vbat_gnd3p3_core1 u9 wrf_pa2g_vbat_vdd3p3_core0 r1 wrf_pa2g_vbat_vdd3p3_core1 v9 wrf_pa5g_vbat_gnd3p3_core0 t2 wrf_pa5g_vbat_gnd3p3_core0 u2 wrf_pa5g_vbat_gnd3p3_core1 u10 wrf_pa5g_vbat_gnd3p3_core1 u11 wrf_pa5g_vbat_vdd3p3_core0 t1 wrf_pa5g_vbat_vdd3p3_core1 v10 wrf_padrv_vbat_gnd3p3_core0 t3 wrf_padrv_vbat_gnd3p3_core1 t10 wrf_padrv_vbat_vdd3p3_core0 r3 wrf_padrv_vbat_vdd3p3_core1 t9 wrf_pfd_gnd1p2 u5 wrf_pfd_vdd1p2 t4 wrf_rfin_2g_core0 n1 wrf_rfin_2g_core1 v7 wrf_rfin_5g_core0 v1 wrf_rfin_5g_core1 v12 wrf_rfout_2g_core0 p1 pin name wlbga ball#
document number: 002-14809 rev. *j page 70 of 165 cyw4354 wrf_rfout_2g_core1 v8 wrf_rfout_5g_core0 u1 wrf_rfout_5g_core1 v11 wrf_rx2g_gnd1p2_core0 n3 wrf_rx2g_gnd1p2_core1 t7 wrf_rx5g_gnd1p2_core0 v3 wrf_rx5g_gnd1p2_core1 t12 wrf_synth_vbat_vdd3p3 v6 wrf_tssi_a_core0 u3 wrf_tssi_a_core1 t11 wrf_tx_gnd1p2_core0 p3 wrf_tx_gnd1p2_core1 t8 wrf_vco_gnd1p2 u6 wrf_xtal_gnd1p2 n11 wrf_xtal_in p12 wrf_xtal_out n12 wrf_xtal_vdd1p2 n10 wrf_xtal_vdd1p5 p11 pin name wlbga ball#
document number: 002-14809 rev. *j page 71 of 165 cyw4354 table 21. 395-bump wlcsp coordinates no. net name coordinates (0,0 center of die) bump side top side x y x y 1 pcie_rxtx_avss 2300.51 3659.87 ?2300.51 3659.87 2 pcie_pll_avss 1966.81 3659.87 ?1966.81 3659.87 3 pcie_refclkp 1966.81 3434.87 ?1966.81 3434.87 4 pcie_refclkn 1800.31 3547.37 ?1800.31 3547.37 5 pcie_tdn0 2134.01 3547.37 ?2134.01 3547.37 6 pcie_tdp0 2134.01 3322.37 ?2134.01 3322.37 7 pcie_rxtx_avdd1p2 2134.01 3068.53 ?2134.01 3068.53 8 pcie_rdp0 2300.51 3209.87 ?2300.51 3209.87 9 pcie_rdn0 2300.51 3434.87 ?2300.51 3434.87 10 pcie_pll_avss 1966.81 3209.87 ?1966.81 3209.87 11 pcie_pll_avdd1p2 1800.31 3322.37 ?1800.31 3322.37 12 usb3_refclkn 508.44 3481.00 ?508.44 3481.00 13 usb3_pvdd1p2 768.62 3062.57 ?768.62 3062.57 14 usb3_refclkp 508.44 3281.00 ?508.44 3281.00 15 usb3_rvdd1p2 1177.22 3062.57 ?1177.22 3062.57 16 usb3_tvdd1p2 972.92 3062.57 ?972.92 3062.57 17 usb3_pgnd 553.11 3681.00 ?553.11 3681.00 18 usb3_pgnd 753.11 3681.00 ?753.11 3681.00 19 usb3_ptestp 773.17 3481.00 ?773.17 3481.00 20 usb3_ptestn 773.17 3281.00 ?773.17 3281.00 21 usb3_tdp 974.72 3481.00 ?974.72 3481.00 22 usb3_tdn 974.72 3281.00 ?974.72 3281.00 23 usb3_tgnd 982.37 3681.00 ?982.37 3681.00 24 usb3_rdp 1176.88 3281.00 ?1176.88 3281.00 25 usb3_rdn 1176.88 3481.00 ?1176.88 3481.00 26 usb3_rgnd 1186.67 3681.00 ?1186.67 3681.00 27 usb3_pvdd1p2 526.91 3062.57 ?526.91 3062.57 28 usb3_dvdd1p2 1177.22 2860.07 ?1177.22 2860.07 29 usb3_dvdd1p2 768.62 2860.07 ?768.62 2860.07 30 usb2_avss 1601.79 3595.19 ?1601.79 3595.19 31 usb2_moncdr 1601.79 2 792.39 ?1601.79 2792.39 32 usb2_rref 1401.09 3394.49 ?1401.09 3394.49 33 usb2_dp 1601.79 3394.49 ?1601.79 3394.49 34 usb2_avdd3p3 1601.79 2993.09 ?1601.79 2993.09 35 usb2_dm 1601.79 3193.79 ?1601.79 3193.79 36 usb2_avdd1p2 1401.09 2792.39 ?1401.09 2792.39 37 usb2_avssbg 1401.09 3595.19 ?1401.09 3595.19 38 usb2_monpll 1401.09 2993.09 ?1401.09 2993.09
document number: 002-14809 rev. *j page 72 of 165 cyw4354 39 usb2_dvss 1401.09 3193.79 ?1401.09 3193.79 40 bt_pavss 2217.95 ?736.50 ?2217.95 ?736.50 41 bt_agpio 2017.95 ?1298.03 ?2017.95 ?1298.03 42 bt_ifvdd1p2 1768.91 ?1298.03 ?1768.91 ?1298.03 43 bt_ifvss 1568.92 ?1298.03 ?1568.92 ?1298.03 44 bt_lnavdd1p2 2228.18 ?392.72 ?2228.18 ?392.72 45 bt_lnavss 1843.60 ?524.82 ?1843.60 ?524.82 46 bt_pavdd2p5 2176.03 ?1164.53 ?2176.03 ?1164.53 47 bt_pllvdd1p2 1768.91 ?223.55 ?1768.91 ?223.55 48 bt_pllvss 1568.92 ?223.55 ?1568.92 ?223.55 49 bt_rf 2252.39 ?936.50 ?2252.39 ?936.50 50 bt_vcovdd1p2 2227.01 ?189.65 ?2227.01 ?189.65 51 bt_vcovss 1967.62 ?45.40 ?1967.62 ?45.40 52 fm_audiovdd1p2 2044. 00 931.81 ?2044.00 931.81 53 fm_audioavss 2044.00 1143.58 ?2044.00 1143.58 54 fm_aout1 2244.00 1 143.58 ?2244.00 1143.58 55 fm_aout2 2244.00 9 31.81 ?2244.00 931.81 56 fm_ifvdd1p2 1614.95 371.79 ?1614.95 371.79 57 fm_ifvss 1614.95 1 71.80 ?1614.95 171.80 58 fm_pllvss 1793.21 8 71.61 ?1793.21 871.61 59 fm_pllvdd1p2 1686.40 695.87 ?1686.40 695.87 60 fm_rfaux 2273.40 68.08 ?2273.40 68.08 61 fm_rfin 2260.02 313.69 ?2260.02 313.69 62 fm_lnavdd1p2 2060.02 354.59 ?2060.02 354.59 63 fm_lnavss 2060.02 154.59 ?2060.02 154.59 64 fm_vcovdd1p2 2273.40 731.81 ?2273.40 731.81 65 fm_vcovss 2273.40 5 31.81 ?2273.40 531.81 66 rf_sw_ctrl_0 ?2202.33 ?1494.00 2202.33 ?1494.00 67 vddc ?661.10 ?1355.99 661.10 ?1355.99 68 vssc 740.99 2052.00 ?740.99 2052.00 69 vssc ?616.50 ?408.01 616.50 ?408.01 70 vssc ?459.00 ?198.00 459.00 ?198.00 71 vssc ?546.71 ?1008.00 546.71 ?1008.00 72 vssc ?546.71 ?708.00 546.71 ?708.00 73 vssc ?459.00 252.00 459.00 252.00 74 vddc ?661.10 ?21.01 661.10 ?21.01 75 vssc 740.99 2352.00 ?740.99 2352.00 76 vddio_sd ?405.00 2299.50 405.00 2299.50 table 21. 395-bump wlcsp coordinates (cont.) no. net name coordinates (0,0 center of die) bump side top side x y x y
document number: 002-14809 rev. *j page 73 of 165 cyw4354 77 sdio_data_1 ?337.05 2531.57 337.05 2531.57 78 sdio_clk ?337.05 2731.57 337.05 2731.57 79 sdio_data_3 ?337.05 2931.58 337.05 2931.58 80 sdio_data_2 ?337.05 3131.59 337.05 3131.59 81 sdio_cmd ?337.05 3331.59 337.05 3331.59 82 sdio_data_0 ?337.05 3531.60 337.05 3531.60 83 vssc ?316.50 ?408.01 316.50 ?408.01 84 vssc ?266.51 ?1008.00 266.51 ?1008.00 85 vssc ?266.51 ?708.00 266.51 ?708.00 86 rf_sw_ctrl_4 ?2072.12 ?1125.00 2072.12 ?1125.00 87 vddc ?261.11 ?21.01 261.11 ?21.01 88 vssc ?259.00 1651.99 259.00 1651.99 89 vssc ?159.00 252.00 159.00 252.00 90 vssc ?159.00 552.00 159.00 552.00 91 vssc ?159.00 851.99 159.00 851.99 92 vssc ?159.00 1151.99 159.00 1151.99 93 vssc ?159.00 1451.99 159.00 1451.99 94 vssc ?159.00 2052.00 159.00 2052.00 95 vssc ?459.00 552.00 459.00 552.00 96 dgndhsic ?67.05 2286.36 67.05 2286.36 97 agnd12pll ?67.05 2486.57 67.05 2486.57 98 avdd12pll ?67.05 2686.57 67.05 2686.57 99 rrefhsic ?67.05 2886.58 67.05 2886.58 100 strobe ?67.05 3086.59 67.05 3086.59 101 data ?67.05 3286.59 67.05 3286.59 102 dvdd12hsic ?67.05 3486.60 67.05 3486.60 103 vddc ?61.11 ?1220.99 61.11 ?1220.99 104 vssc ?61.11 ?1008.00 61.11 ?1008.00 105 vssc ?61.11 ?708.00 61.11 ?708.00 106 vssc ?61.11 ?408.01 61.11 ?408.01 107 vddc ?61.11 ?21.01 61.11 ?21.01 108 vddc ?61.11 1843.97 61.11 1843.97 109 vddc 138.89 ?1220.99 ?138.89 ?1220.99 110 vddc 138.89 ?1021.00 ?138.89 ?1021.00 111 vddc 138.89 ?821.00 ?138.89 ?821.00 112 vddc ?261.11 ?1220.99 261.11 ?1220.99 113 vddc 138.89 ?421.00 ?138.89 ?421.00 114 vddc 138.89 ?221.00 ?138.89 ?221.00 table 21. 395-bump wlcsp coordinates (cont.) no. net name coordinates (0,0 center of die) bump side top side x y x y
document number: 002-14809 rev. *j page 74 of 165 cyw4354 115 vddc 138.89 ?21.01 ?138.89 ?21.01 116 vssc 140.99 252.00 ?140.99 252.00 117 vssc 140.99 552.00 ?140.99 552.00 118 vssc 140.99 851.99 ?140.99 851.99 119 vssc 140.99 1151.99 ?140.99 1151.99 120 vssc 140.99 1451.99 ?140.99 1451.99 121 vssc 140.99 1651.99 ?140.99 1651.99 122 vssc 140.99 2052.00 ?140.99 2052.00 123 packageoption_4 140.99 2352.00 ?140.99 2352.00 124 bt_vssc 768.37 ?1186 .86 ?768.37 ?1186.86 125 bt_vssc 816.40 21.84 ?816.40 21.84 126 bt_vssc 599.69 ?715.49 ?599.69 ?715.49 127 vddc 338.89 443.99 ?338.89 443.99 128 vddc 338.89 643.99 ?338.89 643.99 129 vddc 338.89 1843.97 ?338.89 1843.97 130 vssc ?459.00 851.99 459.00 851.99 131 packageoption_2 440.99 2352.00 ?440.99 2352.00 132 packageoption_3 440.99 2592.00 ?440.99 2592.00 133 bt_vssc 468.37 ?1186 .86 ?468.37 ?1186.86 134 vddc 538.88 643.99 ?538.88 643.99 135 vddc 538.88 843.98 ?538.88 843.98 136 vddc 538.88 1043.98 ?538.88 1043.98 137 vddc 538.88 1243.98 ?538.88 1243.98 138 vddc 538.88 1443.98 ?538.88 1443.98 139 vddc 538.88 1643.98 ?538.88 1643.98 140 vddc 538.88 1843.97 ?538.88 1843.97 141 bt_vddc_iso_1 601.19 ?970.04 ?601.19 ?970.04 142 bt_vddc_iso_2 620.91 ?500.07 ?620.91 ?500.07 143 avdd_bbpll 655.50 1 68.14 ?655. 50 168.14 144 avss_bbpll 655.50 437.48 ?655.50 437.48 145 bt_vddc 1480.37 555.67 ?1480.37 555.67 146 packageoption_1 740.99 2592.00 ?740.99 2592.00 147 bt_vddc 1480.37 780.66 ?1480.37 780.66 148 bt_vddio 830.29 ?445.06 ?830.29 ?445.06 149 bt_vddio 840.29 ?724.53 ?840.29 ?724.53 150 bt_vddio 865.28 ?245.06 ?865.28 ?245.06 151 bt_vddio 915.28 ?973.39 ?915.28 ?973.39 152 packageoption_0 1040.99 2592.00 ?1040.99 2592.00 table 21. 395-bump wlcsp coordinates (cont.) no. net name coordinates (0,0 center of die) bump side top side x y x y
document number: 002-14809 rev. *j page 75 of 165 cyw4354 153 bt_gpio_5 1048.37 420.67 ?1048.37 420.67 154 bt_gpio_3 1048.37 620.67 ?1048.37 620.67 155 bt_gpio_2 1048.37 820.67 ?1048.37 820.67 156 bt_i2s_di 1444.06 1426.01 ?1444.06 1426.01 157 bt_uart_txd 1444.06 1643.00 ?1444.06 1643.00 158 bt_i2s_ws 1143.51 1940.00 ?1143.51 1940.00 159 lpo_in 1143.51 2237.00 ?1143.51 2237.00 160 otp_vdd33 1348.51 2444.00 ?1348.51 2444.00 161 bt_clk_req 1644.06 1426.01 ?1644.06 1426.01 162 bt_uart_rxd 1644.06 1643.00 ?1644.06 1643.00 163 bt_pcm_sync 1343.51 1940.00 ?1343.51 1940.00 164 bt_usb_dn 1343.51 2237.00 ?1343.51 2237.00 165 pcie_pme_l 1548.50 2444.00 ?1548.50 2444.00 166 bt_tm1 1844.06 1346.00 ?1844.06 1346.00 167 bt_i2s_clk 1844.06 1643.00 ?1844.06 1643.00 168 bt_gpio_4 1543.51 1940.00 ?1543.51 1940.00 169 bt_usb_dp 1543.51 2237.00 ?1543.51 2237.00 170 bt_host_wake 2044.05 1346.00 ?2044.05 1346.00 171 bt_i2s_do 2044.05 1643.00 ?2044.05 1643.00 172 bt_uart_cts_n 1743.51 1940.00 ?1743.51 1940.00 173 bt_pcm_in 1743.51 2237.00 ?1743.51 2237.00 174 pcie_clkreq_l 1858.50 2534.00 ?1858.50 2534.00 175 rf_sw_ctrl_1 ?2002.32 ?1494.00 2002.32 ?1494.00 176 bt_dev_wake 2244.05 1346.00 ?2244.05 1346.00 177 bt_pcm_out 2244.05 1643.00 ?2244.05 1643.00 178 bt_uart_rts_n 1943.51 1940.00 ?1943.51 1940.00 179 bt_pcm_clk 1943.51 2237.00 ?1943.51 2237.00 180 perst_l 2058.50 2534.00 ?2058.50 2534.00 181 rf_sw_ctrl_8 ?1945.91 ?806.00 1945.91 ?806.00 182 gpio_13 ?2040.71 5 16.01 2040.71 516.01 183 rf_sw_ctrl_5 ?1872.11 ?1125.00 1872.11 ?1125.00 184 rf_sw_ctrl_12 ?1760.12 ?327.01 1760.12 ?327.01 185 gpio_10 ?1959.30 2 29.01 1959.30 229.01 186 rf_sw_ctrl_2 ?1802.31 ?1494.00 1802.31 ?1494.00 187 rf_sw_ctrl_9 ?1745.90 ?806.00 1745.90 ?806.00 188 gpio_14 ?1840.71 5 16.01 1840.71 516.01 189 gpio_7 ?1853.50 ? 18.00 1853.50 ?18.00 190 rf_sw_ctrl_6 ?1672.10 ?1125.00 1672.10 ?1125.00 table 21. 395-bump wlcsp coordinates (cont.) no. net name coordinates (0,0 center of die) bump side top side x y x y
document number: 002-14809 rev. *j page 76 of 165 cyw4354 191 rf_sw_ctrl_13 ?1560.11 ?327.01 1560.11 ?327.01 192 gpio_11 ?1759.91 2 79.00 1759.91 279.00 193 rf_sw_ctrl_3 ?1602.31 ?1494.00 1602.31 ?1494.00 194 rf_sw_ctrl_10 ?1545.89 ?806.00 1545.89 ?806.00 195 gpio_15 ?1640.70 5 16.01 1640.70 516.01 196 gpio_8 ?1593.91 22.00 1593.91 22.00 197 rf_sw_ctrl_7 ?1472.09 ?1125.00 1472.09 ?1125.00 198 rf_sw_ctrl_14 ?1360.11 ?327.01 1360.11 ?327.01 199 gpio_12 ?1559.91 2 79.00 1559.91 279.00 200 vssc ?459.00 1151.99 459.00 1151.99 201 vssc ?459.00 1451.99 459.00 1451.99 202 rf_sw_ctrl_11 ?1346.09 ?756.00 1346.09 ?756.00 203 vddc ?459.00 1651.99 459.00 1651.99 204 vddc ?1345.37 1017.54 1345.37 1017.54 205 gpio_9 ?1393.90 22.00 1393.90 22.00 206 vddio ?1215.90 5 76.00 1215.90 576.00 207 rf_sw_ctrl_15 ?1160.10 ?327.01 1160.10 ?327.01 208 vddc ?1261.10 1843.97 1261.10 1843.97 209 vddc ?1061.11 ?1156.00 1061.11 ?1156.00 210 vddc ?1061.11 ?776.00 1061.11 ?776.00 211 vddc ?1061.10 ?1355.99 1061.10 ?1355.99 212 vddc_iso_phy ?1402.10 ?1494.00 1402.10 ?1494.00 213 vddc ?1180.10 ?587.00 1180.10 ?587.00 214 vddc_iso_phy ?1151.11 ?956.00 1151.11 ?956.00 215 vddc_iso_dig ?1058.99 2052.00 1058.99 2052.00 216 vddc_iso_dig ?816.10 1843.97 816.10 1843.97 217 vssc ?459.00 2052.00 459.00 2052.00 218 gpio_0 ?996.05 2877.58 996.05 2877.58 219 gpio_1 ?996.05 3077.59 996.05 3077.59 220 gpio_2 ?996.05 3277.59 996.05 3277.59 221 gpio_3 ?996.05 3477.60 996.05 3477.60 222 vddio ?990.90 576.00 990.90 576.00 223 vddio_rf ?960.10 ?117.00 960.10 ?117.00 224 vddc ?1061.10 1843.97 1061.10 1843.97 225 vddc_iso_phy ?1061.10 843.98 1061.10 843.98 226 vddc_iso_phy ?1058.99 1151.99 1058.99 1151.99 227 vddio_rf ?852.10 ?387.00 852.10 ?387.00 228 vddc ?461.11 ?1355.99 461.11 ?1355.99 table 21. 395-bump wlcsp coordinates (cont.) no. net name coordinates (0,0 center of die) bump side top side x y x y
document number: 002-14809 rev. *j page 77 of 165 cyw4354 229 gpio_4 ?769.05 3196.59 769.05 3196.59 230 vddio_pcie a ?759.00 252.00 759.00 252.00 231 vddio ?759.00 552.00 759.00 552.00 232 vssc ?1359.90 279.00 1359.90 279.00 233 vssc ?1319.39 2052.00 1319.39 2052.00 234 vssc ?1358.99 2302.00 1358.99 2302.00 235 vssc ?1351.11 ?956.00 1351.11 ?956.00 236 gpio_6 ?751.05 2996.59 751.05 2996.59 237 gpio_5 ?751.05 3396.60 751.05 3396.60 238 vddio_sd ?745.50 2352.00 745.50 2352.00 239 jtag_sel ?733.05 2796.58 733.05 2796.58 240 vddc_iso_phy ?729.00 ?220.50 729.00 ?220.50 241 vddc ?951.31 ?956.00 951.31 ?956.00 242 vddc ?861.10 ?1355.99 861.10 ?1355.99 243 vssc ?1440.90 576.00 1440.90 576.00 244 vssc ?1159.90 ?98.00 1159.90 ?98.00 245 vssc ?1159.90 279.00 1159.90 279.00 246 vddc ?616.10 1843.97 616.10 1843.97 247 wrf_synth_vbat_vdd3p3 75.91 ?3598.00 ?75.91 ?3598.00 248 wrf_xtal_gnd1p2 ?2003.12 ?1834.98 2003.12 ?1834.98 249 wrf_xtal_vdd1p5 ?2003.12 ?2065.65 2003.12 ?2065.65 250 wrf_vco_gnd1p2 198.52 ?3109.71 ?198.52 ?3109.71 251 wrf_xtal_in ?2205.82 ?2065.65 2205.82 ?2065.65 252 wrf_logen_gnd1p2 126.11 ?2303.63 ?126.11 ?2303.63 253 wrf_xtal_out ?2205.82 ?1818.42 2205.82 ?1818.42 254 wrf_xtal_vdd1p2 ?1807.98 ?1960.54 1807.98 ?1960.54 255 wrf_tx_gnd1p2_core1 ?437.83 ?2417.93 437.83 ?2417.93 256 wrf_buck_gnd1p5_core1 ?2137.36 ?2823.85 2137.36 ?2823.85 257 wrf_rx5g_gnd1p2_core1 ?1968.14 ?2944.01 1968.14 ?2944.01 258 wrf_gpio_out_core1 ?877.08 ?2398.01 877.08 ?2398.01 259 wrf_rx2g_gnd1p2_core1 ?167.27 ?2716.52 167.27 ?2716.52 260 wrf_rfin_5g_core1 ?2253.44 ?3538.14 2253.44 ?3538.14 261 wrf_rfin_2g_core1 ?201.47 ?3598.00 201.47 ?3598.00 262 wrf_pfd_vdd1p2 901.40 ?2994.96 ?901.40 ?2994.96 263 wrf_pfd_gnd1p2 818.12 ?3198.01 ?818.12 ?3198.01 264 wrf_padrv_vbat_vdd3p3_core1 ?1090.70 ?2792.61 1090.70 ?2792.61 265 wrf_padrv_vbat_gnd3p3_core1 ?1401.46 ?2798.01 1401.46 ?2798.01 266 wrf_pa5g_vbat_vdd3p3_core1 ?1401.46 ?3679.00 1401.46 ?3679.00 table 21. 395-bump wlcsp coordinates (cont.) no. net name coordinates (0,0 center of die) bump side top side x y x y
document number: 002-14809 rev. *j page 78 of 165 cyw4354 267 wrf_afe_gnd1p2_core1 ?631.56 ?2293.35 631.56 ?2293.35 268 wrf_pa5g_vbat_gnd3p3_core0 1825.51 ?2798.01 ?1825.51 ?2798.01 269 wrf_pa5g_vbat_vdd3p3_core0 2297.50 ?2998.01 ?2297.50 ?2998.01 270 wrf_mmd_vdd1p2 692.41 ?2994.96 ?692.41 ?2994.96 271 wrf_mmd_gnd1p2 499.12 ?2798.01 ?499.12 ?2798.01 272 wrf_pa2g_vbat_gnd3p3_core0 1744.51 ?1940.22 ?1744.51 ?1940.22 273 wrf_lna_5g_gnd1p2_core0 1877.39 ?3673.49 ?1877.39 ?3673.49 274 wrf_cp_gnd1p2 539.26 ?3598.00 ?539.26 ?3598.00 275 wrf_lna_2g_gnd1p2_core0 1798.51 ?1598.02 ?1798.51 ?1598.02 276 wrf_tssi_a_core1 ?1839.15 ?2716.77 1839.15 ?2716.77 277 wrf_buck_vdd1p5_core0 1024.35 ?3433.91 ?1024.35 ?3433.91 278 wrf_logeng_gnd1p2 770.31 ?2353.01 ?770.31 ?2353.01 279 wrf_rfout_2g_core1 ?601.47 ?3679.00 601.47 ?3679.00 280 wrf_rfout_5g_core0 2288.50 ?3198.01 ?2288.50 ?3198.01 281 wrf_afe_gnd1p2_core0 880.13 ?2028.11 ?880.13 ?2028.11 282 wrf_lna_2g_gnd1p2_core1 ?201.47 ?3198.01 201.47 ?3198.01 283 wrf_lna_5g_gnd1p2_core1 ?2276.94 ?3276.89 2276.94 ?3276.89 284 wrf_pa2g_vbat_gnd3p3_core1 ?543.68 ?3144.01 543.68 ?3144.01 285 wrf_pa2g_vbat_vdd3p3_core1 ?801.47 ?3697.00 801.47 ?3697.00 286 wrf_pa5g_vbat_gnd3p3_core1 ?1801.46 ?3225.01 1801.46 ?3225.01 287 wrf_pa5g_vbat_vdd3p3_core0 2279.50 ?2798.01 ?2279.50 ?2798.01 288 wrf_padrv_vbat_gnd3p3_core0 1398.51 ?2798.01 ?1398.51 ?2798.01 289 wrf_padrv_vbat_vdd3p3_core0 1393.11 ?2487.25 ?1393.11 ?2487.25 290 wrf_rfin_2g_core0 2198.50 ?1598.02 ?2198.50 ?1598.02 291 wrf_rx2g_gnd1p2_core0 1317.02 ?1563.82 ?1317.02 ?1563.82 292 wrf_rx5g_gnd1p2_core0 1544.51 ?3364.69 ?1544.51 ?3364.69 293 wrf_tx_gnd1p2_core0 1018.43 ?1834.38 ?1018.43 ?1834.38 294 wrf_tssi_a_core0 1317.27 ?3235.69 ?1317.27 ?3235.69 295 wrf_buck_gnd1p5_core0 1424.35 ?3533.90 ?1424.35 ?3533.90 296 wrf_buck_vdd1p5_core1 ?2237.36 ?2423.85 2237.36 ?2423.85 297 wrf_gpio_out_core0 998.51 ?2273.63 ?998.51 ?2273.63 298 wrf_rfout_2g_core0 2279.50 ?1998.02 ?2279.50 ?1998.02 299 wrf_rfout_5g_core1 ?1801.46 ?3688.00 1801.46 ?3688.00 300 wrf_pa2g_vbat_gnd3p3_core0 1714.63 ?2523.25 ?1714.63 ?2523.25 301 wrf_pa2g_vbat_gnd3p3_core1 ?1126.70 ?3114.13 1126.70 ?3114.13 302 wrf_rfin_5g_core0 2138.64 ?3649.99 ?2138.64 ?3649.99 303 wrf_pa5g_vbat_gnd3p3_core0 1825.51 ?3198.01 ?1825.51 ?3198.01 304 wrf_pa5g_vbat_gnd3p3_core1 ?1401.46 ?3225.01 1401.46 ?3225.01 table 21. 395-bump wlcsp coordinates (cont.) no. net name coordinates (0,0 center of die) bump side top side x y x y
document number: 002-14809 rev. *j page 79 of 165 cyw4354 305 wrf_pa2g_vbat_vdd3p3_core0 2279.50 ?2398.01 ?2279.50 ?2398.01 306 wrf_pa2g_vbat_vdd3p3_core0 2297.50 ?2198.02 ?2297.50 ?2198.02 307 wrf_rx2g_gnd1p2_core0 1488.79 ?1700.51 ?1488.79 ?1700.51 308 wrf_buck_vdd1p5_core0 1024.35 ?3633.90 ?1024.35 ?3633.90 309 wrf_buck_vdd1p5_core0 1224.35 ?3633.90 ?1224.35 ?3633.90 310 wrf_buck_vdd1p5_core0 1224.35 ?3433.91 ?1224.35 ?3433.91 311 wrf_buck_vdd1p5_core1 ?2037.36 ?2423.85 2037.36 ?2423.85 312 wrf_buck_vdd1p5_core1 ?2037.36 ?2623.85 2037.36 ?2623.85 313 wrf_buck_vdd1p5_core1 ?2237.36 ?2623.85 2237.36 ?2623.85 314 wrf_pa5g_vbat_vdd3p3_core1 ?1601.46 ?3697.00 1601.46 ?3697.00 315 wrf_pa2g_vbat_vdd3p3_core1 ?1001.47 ?3679.00 1001.47 ?3679.00 316 wrf_logen_gnd1p2 326.11 ?2303.63 ?326.11 ?2303.63 317 wrf_rx2g_gnd1p2_core1 ?303.96 ?2888.29 303.96 ?2888.29 318 wrf_cp_gnd1p2 339.26 ?3598.00 ?339.26 ?3598.00 319 wl_reg_on ?1710.77 3277.01 1710.77 3277.01 320 bt_reg_on ?1569.35 1721.37 1569.35 1721.37 321 ldo_vddbat5v ?1852.20 1721.37 1852.20 1721.37 322 ldo_vddbat5v ?1852.20 1438.53 1852.20 1438.53 323 ldo_vddbat5v ?1852.20 1155.69 1852.20 1155.69 324 vout_3p3 ?1993.62 1297.11 1993.62 1297.11 325 vout_3p3 ?2135.04 1155.69 2135.04 1155.69 326 vddio_pmu ?1710.77 1297.11 1710.77 1297.11 327 ldo_vddbat5v ?1852.20 872.84 1852.20 872.84 328 ldo_vddbat5v ?2135.04 872.84 2135.04 872.84 329 ldo_vddbat5v ?2276.46 1014.26 2276.46 1014.26 330 vout_3p3_sense ?2276.46 1297.11 2276.46 1297.11 331 ldo_vddbat5v ?1710.77 1862.79 1710.77 1862.79 332 vout_3p3 ?1993.62 1579.95 1993.62 1579.95 333 vssc ?1569.35 1155.69 1569.35 1155.69 334 vssc ?1569.35 1438.53 1569.35 1438.53 335 pmu_avss ?1569.35 2287.06 1569.35 2287.06 336 sr_vlx ?1569.35 2852.74 1569.35 2852.74 337 sr_vlx ?1569.35 3135.59 1569.35 3135.59 338 sr_pvss ?1852.20 3135.59 1852.20 3135.59 339 sr_vlx ?1852.20 2852.74 1852.20 2852.74 340 sr_vddbata5v ?1852.20 2569.90 1852.20 2569.90 341 vout_cldo ?1852.20 2287.06 1852.20 2287.06 342 ldo_vdd1p5 ?1852.20 2 004.21 1852.20 2004.21 table 21. 395-bump wlcsp coordinates (cont.) no. net name coordinates (0,0 center of die) bump side top side x y x y
document number: 002-14809 rev. *j page 80 of 165 cyw4354 343 ldo_vddbat5v ?1993.62 1014.26 1993.62 1014.26 344 vout_3p3 ?2135.04 1438.53 2135.04 1438.53 345 ldo_vddbat5v ?2135.04 1721.37 2135.04 1721.37 346 vout_ldo3p3_b ?2135.04 2004.21 2135.04 2004.21 347 ldo_vdd1p5 ?2135.04 2 287.06 2135.04 2287.06 348 sr_vddbatp5v ?2135.04 2569.90 2135.04 2569.90 349 sr_pvss ?2135.04 3135.59 2135.04 3135.59 350 vddio_pmu ?1710.77 1579.95 1710.77 1579.95 351 vout_lnldo ?1710.77 2145.64 1710.77 2145.64 352 vout_cldo ?1710.77 2428.48 1710.77 2428.48 353 sr_vlx ?1710.77 2711.32 1710.77 2711.32 354 sr_vlx ?1710.77 2994.17 1710.77 2994.17 355 vout_ldo3p3_b ?1993.62 1862.79 1993.62 1862.79 356 ldo_vdd1p5 ?1993.62 2 145.64 1993.62 2145.64 357 vout_cldo ?1993.62 2428.48 1993.62 2428.48 358 sr_vddbatp5v ?1993.62 2711.32 1993.62 2711.32 359 sr_vlx ?1993.62 2994.17 1993.62 2994.17 360 sr_pvss ?1993.62 3277.01 1993.62 3277.01 361 vout_3p3 ?2276.46 1862.79 2276.46 1862.79 362 vout_btldo2p5 ?2276.46 2145.64 2276.46 2145.64 363 ldo_vdd1p5 ?2276.46 2 428.48 2276.46 2428.48 364 sr_pvss ?2276.46 3277.01 2276.46 3277.01 365 vout_3p3 ?2276.46 1579.95 2276.46 1579.95 366 sr_vddbatp5v ?2276.46 2711.32 2276.46 2711.32 367 pcie_testp 1800.31 3068.53 ?1800.31 3068.53 368 pcie_testn 1966.81 2956.03 ?1966.81 2956.03 369 bt_vddc 1480.37 1005.66 ?1480.37 1005.66 370 bt_vddc 1480.37 1225.66 ?1480.37 1225.66 371 bt_vddc 1408.19 248.05 ?1408.19 248.05 372 bt_vddc 1322.34 55.02 ?1322.34 55.02 373 bt_vddc 1060.28 ?1186.86 ?1060.28 ?1186.86 374 bt_vddc 666.40 ?198.15 ?666.40 ?198.15 375 bt_vddc 617.61 ?1324.61 ?617.61 ?1324.61 376 bt_vssc 338.89 ?475.07 ?338.89 ?475.07 377 bt_vssc 1040.28 ?724.53 ?1040.28 ?724.53 378 bt_vssc 1063.38 1020.66 ?1063.38 1020.66 379 bt_vssc 1063.38 1320.66 ?1063.38 1320.66 380 bt_vssc 1273.37 5 05.67 ?1273. 37 505.67 table 21. 395-bump wlcsp coordinates (cont.) no. net name coordinates (0,0 center of die) bump side top side x y x y
document number: 002-14809 rev. *j page 81 of 165 cyw4354 381 bt_vssc 1273.37 7 05.66 ?1273. 37 705.66 382 bt_vssc 1273.37 1005.66 ?1273.37 1005.66 383 bt_vssc 1273.37 1225.66 ?1273.37 1225.66 384 vssc 440.99 2052.00 ?440.99 2052.00 385 vssc ?1293.24 ?1317.60 1293.24 ?1317.60 386 vssc ?1202.10 ?1504.00 1202.10 ?1504.00 387 vssc ?1058.99 1451.99 1058.99 1451.99 388 vssc ?1058.99 2302.00 1058.99 2302.00 389 vssc ?959.90 279.00 959.90 279.00 390 vssc ?759.00 851.99 759.00 851.99 391 vssc ?759.00 1151.99 759.00 1151.99 392 vssc ?759.00 1451.99 759.00 1451.99 393 vssc ?759.00 2052.00 759.00 2052.00 394 vssc ?746.31 ?956.00 746.31 ?956.00 395 vssc ?746.31 ?756.00 746.31 ?756.00 a. this net name was changed to vddio_pcie to correct an error in the pin definition of bump 230. the correction applies to wlcs p package pcie platform only, and is in consequential for sdio platforms. table 21. 395-bump wlcsp coordinates (cont.) no. net name coordinates (0,0 center of die) bump side top side x y x y
document number: 002-14809 rev. *j page 82 of 165 cyw4354 13.3 signal descriptions the signal name, type, and description of each pin in the cyw4354 is listed in ta b l e 2 2 (wlcsp) and table 23 on page 89 (wlbga). the symbols shown under type indicate pin directions (i/o = bidi rectional, i = input, o = output) and the internal pull-up/pull -down characteristics (pu = weak internal pull-up resistor and pd = weak internal pull-down resistor), if any. table 22. wlcsp signal descriptions bump# signal name type description wlan and bluetooth receive rf signal interface 290 wrf_rfin_2g_core0 i 2.4 ghz bluetooth and wlan core0 receiver shared input 261 wrf_rfin_2g_core1 i 2.4 ghz bluetooth and wlan core1 receiver shared input 302 wrf_rfin_5g_core0 i 5 ghz wlan core0 receiver input 260 wrf_rfin_5g_core1 i 5 ghz wlan core1 receiver input 298 wrf_rfout_2g_core0 o 2.4 ghz wlan core0 pa output 279 wrf_rfout_2g_core1 o 2.4 ghz wlan core1 pa output 280 wrf_rfout_5g_core0 o 5 ghz wlan core0 pa output 299 wrf_rfout_5g_core1 o 5 ghz wlan core1 pa output 294 wrf_tssi_a_core0 i 5 ghz tssi core0 input from an optional external power amplifier/power detector. 276 wrf_tssi_a_core1 i 5 ghz tssi core1 input from an optional external power amplifier/power detector. 297 wrf_gpio_out_core0 i/o gpio or 2.4 ghz t ssi core0 input from an optional external power amplifier/power detector 258 wrf_gpio_out_core1 i/o gpio or 2.4 ghz t ssi core1 input from an optional external power amplifier/power detector rf switch control lines 66 rf_sw_ctrl_0 o programmable rf switch control lines. the control lines are programmable via the driver and nvram file. 175 rf_sw_ctrl_1 o 186 rf_sw_ctrl_2 o 193 rf_sw_ctrl_3 o 86 rf_sw_ctrl_4 o 183 rf_sw_ctrl_5 o 190 rf_sw_ctrl_6 o 197 rf_sw_ctrl_7 o 181 rf_sw_ctrl_8 o 187 rf_sw_ctrl_9 o 194 rf_sw_ctrl_10 o 202 rf_sw_ctrl_11 o 184 rf_sw_ctrl_12 o 191 rf_sw_ctrl_13 o 198 rf_sw_ctrl_14 o 207 rf_sw_ctrl_15 o wlan pci express interface 174 pcie_clkreq_l od pcie clock request signal which indicates when the refclk to the pcie interface can be gated. 1 = the clock can be gated 0 = the clock is required
document number: 002-14809 rev. *j page 83 of 165 cyw4354 180 pcie_perst_l i (pu) pcie system reset. th is input is the pcie reset as defined in the pcie base specification version 1.1. 9 pcie_rdn0 i receiver differential pair (1 lane) 8 pcie_rdp0 i 4 pcie_refclkn i pcie differential clock inputs (negative and positive). 100 mhz differential. 3 pcie_refclkp i 5 pcie_tdn0 o transmitter differential pair (1 lane) 6pcie_tdp0 o 165 pcie_pme_l od pci power management ev ent output. used to request a change in the device or system powe r state. the assertion and deassertion of this signal is asynchronous to the pcie reference clock. this signal has an open-drai n output structur e, as per the pci bus local bus specification, revision 2.3. 367 pcie_testp ? pcie test pin 368 pcie_testn ? wlan sdio bus interface these signals can support alternat e functionality depending on pack age and host interface mode. see table 27 on page 97 78 sdio_clk i sdio clock input 81 sdio_cmd i/o sdio command line 82 sdio_data_0 i/o sdio data line 0 77 sdio_data_1 i/o sdio data line 1 80 sdio_data_2 i/o sdio data line 2 79 sdio_data_3 i/o sdio data line 3 wlan hsic interface 100 hsic_strobe i/o hsic strobe 101 hsic_data i/o hsic data 99 rrefhsic i hsic reference resistor input . if hsic is used, connect this pin to ground via a 51-ohm 5% resistor. on sdio designs this pin should not be connected. table 22. wlcsp signal descriptions (cont.) bump# signal name type description
document number: 002-14809 rev. *j page 84 of 165 cyw4354 wlan gpio interface the gpio signals can be multiplexed via software and the jtag_sel pin to support other functions. see table 24 on page 96 and table 27 on page 97 for additional details. 218 gpio_0 i/o programmable gpio pins 219 gpio_1 i/o 220 gpio_2 i/o 221 gpio_3 i/o 229 gpio_4 i/o 237 gpio_5 i/o 236 gpio_6 i/o 189 gpio_7 i/o 196 gpio_8 i/o 205 gpio_9 i/o 185 gpio_10 i/o 192 gpio_11 i/o 199 gpio_12 i/o 182 gpio_13 i/o 188 gpio_14 i/o 195 gpio_15 i/o jtag interface 239 jtag_sel i/o jtag select: pull high to se lect the jtag interf ace. if the jtag interface is not used this pin may be left floating or connected to ground. note: see table 27 on page 97 for the jtag signal pins. clocks 251 wrf_xtal_in i xtal oscillator input 253 wrf_xtal_out o xtal oscillator output 159 lpo_in i external sleep clock input (32.768 khz) 161 clk_req o reference clock request (shared by bt and wlan). if not used, this can be no-connect. bluetooth/fm transceiver 49 bt_rf o bluetooth pa output ? bt_sf_clk i sflash_clk ? bt_sf_cs_l i/o sflash_csn ? bt_sf_miso i/o sflash master input, slave output ? bt_sf_mosi i/o sflash master output, slave input 61 fm_rfin i fm radio antenna port 60 fm_rfaux i fm radio auxiliary antenna port 54 fm_aout1 o fm dac output 1 55 fm_aout2 o fm dac output 2 table 22. wlcsp signal descriptions (cont.) bump# signal name type description
document number: 002-14809 rev. *j page 85 of 165 cyw4354 bluetooth pcm 179 bt_pcm_clk i/o pcm clock; can be master (output) or slave (input) 173 bt_pcm_in i pcm data input 177 bt_pcm_out o pcm data output 163 bt_pcm_sync i/o pcm sync; can be ma ster (output) or slave (input). bluetooth usb interface 164 bt_usb_dn i/o usb (host) data negativ e. negative terminal of the usb trans- ceiver. 169 bt_usb_dp i/o usb (host) data positive. positive terminal of the usb trans- ceiver. bluetooth uart 172 bt_uart_cts_l i uart clear-to-send. acti ve-low clear-to-send signal for the hci uart interface. 178 bt_uart_rts_l o uart request-to-send. active-low request-to-send signal for the hci uart interface. bt led control pin. 162 bt_uart_rxd i uart serial input. serial data input for the hci uart interface. 157 bt_uart_txd o uart serial output. serial data output for the hci uart interface. bluetooth/fm i 2 s 167 bt_i2s_clk i/o i 2 s clock, can be master (output) or slave (input). 171 bt_i2s_do i/o i 2 s data output 156 bt_i2s_di i/o i 2 s data input 158 bt_i2s_ws i/o i 2 s ws; can be master ( output) or slave (input). bluetooth gpios 155 bt_gpio_2 i/o bluetooth general-purpose i/o 154 bt_gpio_3 i/o bluetooth general-purpose i/o 168 bt_gpio_4 i/o bluetooth general-purpose i/o 153 bt_gpio_5 i/o bluetooth general-purpose i/o miscellaneous 319 wl_reg_on i used by pmu to power up or power down the internal cyw4354 regulators used by the wlan section. also, when deasserted, this pin holds the wlan section in reset. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. 320 bt_reg_on i used by pmu to power up or power down the internal cyw4354 regulators used by the bluetooth/fm section. also, when deasserted, this pin holds the bluetooth/fm section in reset. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. 176 bt_dev_wake i/o b luetooth dev_wake 170 bt_host_wake i/o bluetooth host_wake table 22. wlcsp signal descriptions (cont.) bump# signal name type description
document number: 002-14809 rev. *j page 86 of 165 cyw4354 integrated voltage regulators 340 sr_vddbata5v i quiet vbat 348 sr_vddbatp5v i power vbat 336 sr_vlx o cbuck switching regulator output. refer to table 44 on page 132 for details of the inductor and capacitor required on this output. 342 ldo_vdd1p5 i lnldo input 327 ldo_vddbat5v i ldo vbat. 249 wrf_xtal_vdd1p5 i xtal ldo input (1.35v) 254 wrf_xtal_vdd1p2 o xtal ldo output (1.2v) 351 vout_lnldo o output of lnldo 341 vout_cldo o output of core ldo 362 vout_btldo2p5 o output of bt ldo 346 vout_ldo3p3_b o output of 3.3v ldo 324 vout_3p3 o ldo 3.3v output 330 vout_3p3_sense o voltage sense pin for ldo 3.3v output bluetooth supplies 46 bt_pavdd2p5 pwr bluetooth pa power supply 44 bt_lnavdd1p2 pwr bluetooth lna power supply 42 bt_ifvdd1p2 pwr bluetooth if block power supply 47 bt_pllvdd1p2 pwr bluetooth rf pll power supply 50 bt_vcovdd1p2 pwr bluetooth rf power supply 148, 149, 150,151 bt_vddio pwr core supply fm transceiver supplies ? fm_lnavcovdd1p2 pwr fm lna and vco 1.2v power supply 62 fm_lnavdd1p2 pwr fm lna 1.2v power supply 64 fm_vcovdd1p2 pwr fm vco 1.2v power supply 59 fm_pllvdd1p2 pwr fm pll 1.2v power supply 52 fm_audiovdd1p2 pwr fm audio power supply wlan supplies 277 wrf_buck_vdd1p5_core0 pwr internal capacitor-less core0 ldo supply 296 wrf_buck_vdd1p5_core1 pwr internal capacitor-less core1 ldo supply 262 wrf_synth_vbat_vdd3p3 pw r synth vdd 3.3v supply 289 wrf_padrv_vbat_vdd3p3_core0 pw r core0 pa driver vbat supply 264 wrf_padrv_vbat_vdd3p3_core1 pw r core1 pa driver vbat supply 269 wrf_pa5g_vbat_vdd3p3_core0 pwr 5 ghz core0 pa 3.3v vbat supply 266 wrf_pa5g_vbat_vdd3p3_core1 pwr 5 ghz core1 pa 3.3v vbat supply 305 wrf_pa2g_vbat_vdd3p3_core0 pwr 2 ghz core0 pa 3.3v vbat supply 285 wrf_pa2g_vbat_vdd3p3_core1 pwr 2 ghz core1 pa 3.3v vbat supply 270 wrf_mmd_vdd1p2 pwr 1.2v supply table 22. wlcsp signal descriptions (cont.) bump# signal name type description
document number: 002-14809 rev. *j page 87 of 165 cyw4354 262 wrf_pfd_vdd1p2 pwr 1.2v supply miscellaneous supplies 160 otp_vdd33 pwr otp 3.3v supply 67, 74, 87, 103, 107? 115, 127? 129, 134? 140, 203, 204, 208? 211, 213, 224, 228, 241, 242, 246 vddc pwr 1.2v core supply for wlan 206, 222, 231 vddio pwr 1.8v?3.3v supply for wlan. must be directly connected to pmu_vddio and bt_vddio on the pcb. 145, 147, 369? 375, bt_vddc pwr 1.2v core supply for bt 326 vddio_pmu pwr 1.8v?3.3v supply for pmu c ontrols. must be directly connected to vddio and bt_vddio on the pcb. 76 vddio_sd pwr 1.8v?3.3v supply for sdio pads 223 vddio_rf pwr io supply for rf switch control pads (3.3v) 98 hsic_avdd12pll pwr 1.2v supply for hsic pll 102 hsic_dvdd12 pwr 1.2v supply for hsic digital 143 avdd_bbpll pwr baseband pll supply 11 pcie_pll_avdd1p2 pwr 1.2v supply for pcie pll 7 pcie_rxtx_avdd1p2 pwr 1.2v supply for pcie tx and rx 230 vddio_pcie pwr supply the same voltage to this pin as used for the pcie out-of- band signals (that is, pcie_pme_l). this would be 1.8v or 3.3v, and cannot be turned off. ground 250 wrf_vco_gnd1p2 gnd vco/logen ground 281 wrf_afe_gnd1p2_core0 gnd core0 afe ground 267 wrf_afe_gnd1p2_core1 gnd core1 afe ground 295 wrf_buck_gnd1p5_core0 gnd internal capacitor-less core0 ldo ground 256 wrf_buck_gnd1p5_core1 gnd internal capacitor-less core1 ldo ground 275 wrf_lna_2g_gnd1p2_core0 gnd 2 ghz internal core0 lna ground 282 wrf_lna_2g_gnd1p2_core1 gnd 2 ghz internal core1 lna ground 273 wrf_lna_5g_gnd1p2_core0 gnd 5 ghz internal core0 lna ground 283 wrf_lna_5g_gnd1p2_core1 gnd 5 ghz internal core1 lna ground 293 wrf_tx_gnd1p2_core0 gnd tx core0 ground 255 wrf_tx_gnd1p2_core1 gnd tx core1 ground 288 wrf_padrv_vbat_gnd3p3_core0 gnd pad core0 ground 265 wrf_padrv_vbat_gnd3p3_core1 gnd pad core1 ground 248 wrf_xtal_gnd1p2 gnd xtal ground table 22. wlcsp signal descriptions (cont.) bump# signal name type description
document number: 002-14809 rev. *j page 88 of 165 cyw4354 291, 307 wrf_rx2g_gnd1p2_core0 gnd rx 2ghz core0 ground 259, 317 wrf_rx2g_gnd1p2_core1 gnd rx 2ghz core1 ground 292 wrf_rx5g_gnd1p2_core0 gnd rx 5ghz core0 ground 257 wrf_rx5g_gnd1p2_core1 gnd rx 5ghz core1 ground 252, 316 wrf_logen_gnd1p2 gnd logen ground 278 wrf_logeng_gnd1p2 gnd logen ground 268, 030 wrf_pa5g_vbat_gnd3p3_core0 gnd 5 ghz pa core0 ground 286, 304 wrf_pa5g_vbat_gnd3p3_core1 gnd 5 ghz pa core1 ground 272, 300 wrf_pa2g_vbat_gnd3p3_core0 gnd 2 ghz pa core0 ground 284, 301 wrf_pa2g_vbat_gnd3p3_core1 gnd 2 ghz pa core1 ground 271 wrf_mmd_gnd1p2 gnd ground 274, 318 wrf_cp_gnd1p2 gnd ground 263 wrf_pfd_gnd1p2 gnd ground 68?73, 75, 83?85, 88?95, 104?106, 116?122, 130, 200, 201, 217, 232?235, 254?245, 333, 334, 384?395 vssc gnd core ground for wlan and bt 338, 349, 360, 364 sr_pvss gnd power ground 335 pmu_avss gnd quiet ground 97 hsic_agnd12pll gnd hsic pll ground 40 bt_pavss gnd bluetooth pa ground 43 bt_ifvss gnd bluetooth if block ground 48 bt_pllvss gnd bluetooth pll ground 51 bt_vcovss gnd bluetooth vco ground 65 fm_vcovss gnd fm vco ground 63 fm_lnavss gnd fm lna ground 58 fm_pllvss gnd fm pll ground 53 fm_audiovss gnd fm audio ground 144 avss_bbpll gnd baseband pll ground 10 pcie_avss gnd pcie ground 1 pcie_rxtx_avss gnd pcie ground 2 pcie_pll_avss gnd pcie ground 17, 18, 23, 26, 96 rgnd gnd ground ? btrgnd gnd ground table 22. wlcsp signal descriptions (cont.) bump# signal name type description
document number: 002-14809 rev. *j page 89 of 165 cyw4354 table 23. wlbga signal descriptions ball# signal name type description wlan and bluetooth receive rf signal interface n1 wrf_rfin_2g_core0 i 2.4 ghz bluetooth and wlan core0 receiver shared input v7 wrf_rfin_2g_core1 i 2.4 ghz bluetooth and wlan core1 receiver shared input v1 wrf_rfin_5g_core0 i 5 ghz wlan core0 receiver input v12 wrf_rfin_5g_core1 i 5 ghz wlan core1 receiver input p1 wrf_rfout_2g_core0 o 2.4 ghz wlan core0 pa output v8 wrf_rfout_2g_core1 o 2.4 ghz wlan core1 pa output u1 wrf_rfout_5g_core0 o 5 ghz wlan core0 pa output v11 wrf_rfout_5g_core1 o 5 ghz wlan core1 pa output u3 wrf_tssi_a_core0 i 5 ghz tssi core0 input from an optional external power amplifier/power detector. t11 wrf_tssi_a_core1 i 5 ghz tssi core1 input from an optional external power amplifier/power detector. r4 wrf_gpio_out_core0 i/o gpio or 2.4 ghz t ssi core0 input from an optional external power amplifier/power detector r9 wrf_gpio_out_core1 i/o gpio or 2.4 ghz t ssi core1 input from an optional external power amplifier/power detector rf switch control lines r7 rf_sw_ctrl_0 o programmable rf switch control lines. the control lines are programmable via the driver and nvram file. n8 rf_sw_ctrl_1 o p9 rf_sw_ctrl_2 o n7 rf_sw_ctrl_3 o n5 rf_sw_ctrl_4 o p7 rf_sw_ctrl_5 o p5 rf_sw_ctrl_6 o m8 rf_sw_ctrl_7 o k12 rf_sw_ctrl_8 o j11 rf_sw_ctrl_9 o m12 rf_sw_ctrl_10 o l9 rf_sw_ctrl_11 o j9 rf_sw_ctrl_12 o k10 rf_sw_ctrl_13 o m10 rf_sw_ctrl_14 o l8 rf_sw_ctrl_15 o wlan pci express interface d5 pcie_clkreq_l od pcie clock request signal which indicates when the refclk to the pcie interface can be gated. 1 = the clock can be gated 0 = the clock is required c4 pcie_perst_l i (pu) pcie system reset. this input is the pcie reset as defined in the pcie base specification version 1.1.
document number: 002-14809 rev. *j page 90 of 165 cyw4354 b1 pcie_rdn0 i receiver differential pair (1 lane) c1 pcie_rdp0 i a5 pcie_refclkn i pcie differential clock inputs (negative and positive). 100 mhz differential. a4 pcie_refclkp i a3 pcie_tdn0 o transmitter differential pair (1 lane) a2 pcie_tdp0 o c5 pcie_pme_l od pci power management event output. used to request a change in the device or system power state. the assertion and deassertion of this signal is asyn chronous to the pcie reference clock. this signal has an open-drai n output structur e, as per the pci bus local bus specification, revision 2.3. c3 pcie_testp ? pcie test pin c2 pcie_testn ? wlan sdio bus interface note: these signals can support alternate functionality d epending on package and host interface mode. see table 27 on page 97 for additional details. a8 sdio_clk i sdio clock input a9 sdio_cmd i/o sdio command line b9 sdio_data_0 i/o sdio data line 0 c9 sdio_data_1 i/o sdio data line 1 b8 sdio_data_2 i/o sdio data line 2 c8 sdio_data_3 i/o sdio data line 3 wlan hsic interface a7 hsic_strobe i/o hsic strobe a6 hsic_data i/o hsic data d7 rrefhsic i hsic reference resistor input. if hsic is used, connect this pin to ground via a 51-ohm 5% resistor. on sdio designs this pin should not be connected. table 23. wlbga signal descriptions ball# signal name type description
document number: 002-14809 rev. *j page 91 of 165 cyw4354 wlan gpio interface note: the gpio signals can be multiplexe d via software and the jtag_sel pin to support other functions. see ta b l e 24 on page 96 and table 27 on page 97 for additional details. g11 gpio_0 i/o programmable gpio pins f10 gpio_1 i/o f11 gpio_2 i/o g9 gpio_3 i/o h9 gpio_4 i/o f9 gpio_5 i/o f8 gpio_6 i/o e7 gpio_7 i/o f7 gpio_8 i/o e6 gpio_9 i/o h12 gpio_10 i/o ? gpio_11 i/o ? gpio_12 i/o ? gpio_13 i/o ? gpio_14 i/o ? gpio_15 i/o jtag interface d9 jtag_sel i/o jtag select: pull high to select the jtag interface. if the jtag interface is not used this pin may be left floating or connected to ground. note : see table 27 on page 97 for the jtag signal pins. clocks p12 wrf_xtal_in i xtal oscillator input n12 wrf_xtal_out o xtal oscillator output f6 lpo_in i external sleep clock input (32.768 khz) f4 clk_req o reference clock request (shar ed by bt and wlan). if not used, this can be no-connect. bluetooth/fm transceiver l1 bt_rf o bluetooth pa output ? bt_sf_clk i sflash_clk ? bt_sf_cs_l i/o sflash_csn ? bt_sf_miso i/o sflash master input, slave output ? bt_sf_mosi i/o sflash master output, slave input h1 fm_rfin i fm radio antenna port ? fm_rfaux i fm radio auxiliary antenna port e1 fm_aout1 o fm dac output 1 f1 fm_aout2 o fm dac output 2 bluetooth pcm table 23. wlbga signal descriptions ball# signal name type description
document number: 002-14809 rev. *j page 92 of 165 cyw4354 m6 bt_pcm_clk i/o pcm clock; can be master (output) or slave (input) j4 bt_pcm_in i pcm data input h4 bt_pcm_out o pcm data output k6 bt_pcm_sync i/o pcm sync; can be master (output) or slave (input). bluetooth usb interface e5 bt_usb_dn i/o usb (host) data negative. negative terminal of the usb trans- ceiver. f5 bt_usb_dp i/o usb (host) data positive. positive terminal of the usb trans- ceiver. bluetooth uart l5 bt_uart_cts_l i uart clear-to-send. active-low clear-to-send signal for the hci uart interface. k5 bt_uart_rts_l o uart request-to-send. active-low request-to-send signal for the hci uart interface. bt led control pin. h5 bt_uart_rxd i uart serial input. serial data input for the hci uart interface. j5 bt_uart_txd o uart serial output. se rial data output for the hci uart interface. bluetooth/fm i 2 s j6 bt_i2s_clk i/o i 2 s clock, can be master (output) or slave (input). g6 bt_i2s_do i/o i 2 s data output g5 bt_i2s_di i/o i 2 s data input l6 bt_i2s_ws i/o i 2 s ws; can be master (output) or slave (input). bluetooth gpio ? bt_gpio_2 i/o bluetooth general-purpose i/o ? bt_gpio_3 i/o bluetooth general-purpose i/o k4 bt_gpio_4 i/o bluetooth general-purpose i/o ? bt_gpio_5 i/o bluetooth general-purpose i/o miscellaneous a10 wl_reg_on i used by pmu to power up or power down the internal cyw4354 regulators used by the wlan section. also, when deasserted, this pin holds the wlan section in reset. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. d10 bt_reg_on i used by pmu to power up or power down the internal cyw4354 regulators used by the bluet ooth/fm section. also, when deasserted, this pin holds the bluetooth/fm section in reset. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. l4 bt_dev_wake i/o bluetooth dev_wake j3 bt_host_wake i/o b luetooth host_wake table 23. wlbga signal descriptions ball# signal name type description
document number: 002-14809 rev. *j page 93 of 165 cyw4354 integrated voltage regulators b11 sr_vddbata5v i quiet vbat b12 sr_vddbatp5v i power vbat a11 sr_vlx o cbuck switching regulator output. refer to table 44 on page 132 for details of the inductor and c apacitor required on this output. c12 ldo_vdd1p5 i lnldo input e12 ldo_vddbat5v i ldo vbat. p11 wrf_xtal_vdd1p5 i xtal ldo input (1.35v) n10 wrf_xtal_vdd1p2 o xtal ldo output (1.2v) d11 vout_lnldo o output of lnldo c11 vout_cldo o output of core ldo d12 vout_btldo2p5 o output of bt ldo e11 vout_ldo3p3_b o output of 3.3v ldo f12 vout_3p3 o ldo 3.3v output ? vout_3p3_sense o voltage sense pin for ldo 3.3v output bluetooth supplies m1 bt_pavdd2p5 pwr bluetooth pa power supply k1 bt_lnavdd1p2 pwr bluetooth lna power supply k3 bt_ifvdd1p2 pwr bluetooth if block power supply k2 bt_pllvdd1p2 pwr bluetooth rf pll power supply j1 bt_vcovdd1p2 pwr bluetooth rf power supply k7 bt_vddio pwr core supply fm transceiver supplies g1 fm_lnavcovdd1p2 pwr fm lna and vco 1.2v power supply ? fm_lnavdd1p2 pwr fm lna 1.2v power supply ? fm_vcovdd1p2 pwr fm vco 1.2v power supply f3 fm_pllvdd1p2 pwr fm pll 1.2v power supply e2 fm_audiovdd1p2 pwr fm audio power supply wlan supplies u4 wrf_buck_vdd1p5_core0 pwr internal capacitor-less core0 ldo supply r11 wrf_buck_vdd1p5_core1 pwr internal capacitor-less core1 ldo supply v6 wrf_synth_vbat_vdd3p3 pwr synth vdd 3.3v supply r3 wrf_padrv_vbat_vdd3p3_core0 pwr core0 pa driver vbat supply t9 wrf_padrv_vbat_vdd3p3_core1 pwr core1 pa driver vbat supply t1 wrf_pa5g_vbat_vdd3p3_core0 pwr 5 ghz core0 pa 3.3v vbat supply v10 wrf_pa5g_vbat_vdd3p3_core1 pwr 5 ghz core1 pa 3.3v vbat supply r1 wrf_pa2g_vbat_vdd3p3_core0 pwr 2 ghz core0 pa 3.3v vbat supply v9 wrf_pa2g_vbat_vdd3p3_core1 pwr 2 ghz core1 pa 3.3v vbat supply t5 wrf_mmd_vdd1p2 pwr 1.2v supply t4 wrf_pfd_vdd1p2 pwr 1.2v supply table 23. wlbga signal descriptions ball# signal name type description
document number: 002-14809 rev. *j page 94 of 165 cyw4354 miscellaneous supplies ? otp_vdd33 pwr otp 3.3v supply b7, d4, e9, g10, j8, j12, l10, m7 vddc pwr 1.2v core supply for wlan e10 vddio pwr 1.8v?3.3v supply for wlan . must be directly connected to pmu_vddio and bt_v ddio on the pcb. e4, h3, m5 bt_vddc pwr 1.2v core supply for bt ? vddio_pmu pwr 1.8v?3.3v supply for pmu co ntrols. must be directly connected to vddio and bt_vddio on the pcb. e8 vddio_sd pwr 1.8v?3.3v supply for sdio pads h11 vddio_rf pwr io supply for rf switch control pads (3.3v) c7 hsic_avdd12pll pwr 1.2v supply for hsic pll c6 hsic_dvdd12 pwr 1.2v supply for hsic digital h7 avdd_bbpll pwr baseband pll supply b3 pcie_pll_avdd1p2 pwr 1.2v supply for pcie pll b2 pcie_rxtx_avdd1p2 pwr 1.2v supply for pcie tx and rx ground u6 wrf_vco_gnd1p2 gnd vco/logen ground p4 wrf_afe_gnd1p2_core0 gnd core0 afe ground r8 wrf_afe_gnd1p2_core1 gnd core1 afe ground v4 wrf_buck_gnd1p5_core0 gnd internal capacitor-less core0 ldo ground r12 wrf_buck_gnd1p5_core1 gnd internal capacitor-less core1 ldo ground n2 wrf_lna_2g_gnd1p2_core0 gnd 2 ghz internal core0 lna ground u7 wrf_lna_2g_gnd1p2_core1 gnd 2 ghz internal core1 lna ground v2 wrf_lna_5g_gnd1p2_core0 gnd 5 ghz internal core0 lna ground u12 wrf_lna_5g_gnd1p2_core1 gnd 5 ghz internal core1 lna ground p3 wrf_tx_gnd1p2_core0 gnd tx core0 ground t8 wrf_tx_gnd1p2_core1 gnd tx core1 ground t3 wrf_padrv_vbat_gnd3p3_core0 gnd pad core0 ground t10 wrf_padrv_vbat_gnd3p3_core1 gnd pad core1 ground n11 wrf_xtal_gnd1p2 gnd xtal ground n3 wrf_rx2g_gnd1p2_core0 gnd rx 2ghz core0 ground t7 wrf_rx2g_gnd1p2_core1 gnd rx 2ghz core1 ground v3 wrf_rx5g_gnd1p2_core0 gnd rx 5ghz core0 ground t12 wrf_rx5g_gnd1p2_core1 gnd rx 5ghz core1 ground r6 wrf_logen_gnd1p2 gnd logen ground r5 wrf_logeng_gnd1p2 gnd logen ground t2, u2 wrf_pa5g_vbat_gnd3p3_core0 gnd 5 ghz pa core0 ground u10, u11 wrf_pa5g_vbat_gnd3p3_core1 gnd 5 ghz pa core1 ground table 23. wlbga signal descriptions ball# signal name type description
document number: 002-14809 rev. *j page 95 of 165 cyw4354 p2, r2 wrf_pa2g_vbat_gnd3p3_core0 gnd 2 ghz pa core0 ground u8, u9 wrf_pa2g_vbat_gnd3p3_core1 gnd 2 ghz pa core1 ground t6 wrf_mmd_gnd1p2 gnd ground v5 wrf_cp_gnd1p2 gnd ground u5 wrf_pfd_gnd1p2 gnd ground c10, d3, d6, g4, g8, g12, l7, l11, m4 vssc gnd core ground for wlan and bt a12 sr_pvss gnd power ground b10 pmu_avss gnd quiet ground b6 hsic_agnd12pll gnd hsic pll ground l2 bt_pavss gnd bluetooth pa ground m3 bt_ifvss gnd bluetooth if block ground l3 bt_pllvss gnd bluetooth pll ground j2 bt_vcovss gnd bluetooth vco ground g2 fm_vcovss gnd fm vco ground h2 fm_lnavss gnd fm lna ground g3 fm_pllvss gnd fm pll ground f2 fm_audiovss gnd fm audio ground g7 avss_bbpll gnd baseband pll ground ? pcie_avss gnd pcie ground b4 pcie_rxtx_avss gnd pcie ground b5 pcie_pll_avss gnd pcie ground ? rgnd gnd ground ? btrgnd gnd ground table 23. wlbga signal descriptions ball# signal name type description
document number: 002-14809 rev. *j page 96 of 165 cyw4354 13.4 wlan/bt gpio signals and strapping options the pins listed in table 24 and table 25 are sampled at power-on reset (por) to determine the various operating modes. sampling occurs a few milliseconds after an internal por or deassertion of the external por. after the por, each pin assumes the gpio or alternative function specif ied in the signal descriptions table. each strapping option pin has an internal pull-up (pu) or pull -down (pd) resistor that determines the default mode. to change the mode, connect an external pu resi stor to vddio or a pd resistor to gnd , using a 10 k ? resistor or less. note: refer to the reference board schematics for more information. table 24. wlan gpio functions and strapping options pin name default function description gpio_4 0 1: sprom is present 0: sprom is absent (default). applicable in pcie host mode. note : in sdio host mode, sdiopadvddio is 3.3v while set to 1, and 1.8v while set to 0. gpio_5 0 0: sflash absent (default) 1: sflash present gpio_[10, 9, 8] [0,0,0] host interface selection: see ta b l e 2 6 . gpio_12 1 1 = htavailable (default) 0 = resourcemodeinit is alpavailable. on pcbs, use a pull-down and tie to alp clock mode. table 25. bt gpio functions and strapping options pin name default function description bt_gpio4 0 1: bt serial flash is present. 0: bt serial flash is absent (default) table 26. gpio_[10, 9, 8] host interface selection gpio_[10, 9, 8] bit setting wlan host in terface mode bluetooth mode 000 sdio btuart or btusb; bt tports stand-alone. 010 hsic_30d btuart or btusb; bt tports stand-alone 011 pcie btuart or btusb; bt tports stand-alone
document number: 002-14809 rev. *j page 97 of 165 cyw4354 13.5 gpio alternative signal functions table 27. gpio alternative signal functions test mode uart sflash sprom bsc miscella- neous-0 (jtag_sel = 1) gci miscellaneous- 1 miscella- neous-2 pwdog pin names function select additional functionality 0 2 3 4 5 6 7 8 9 10 gpio_0 test_gpio_0 fast_uar t _rx uart_dbg _tx ? bsc_clk ? gci_g- pio_4 sdio_sep_int sdio_sep_int _od pwdog _gpio_0 wl_host_wak e gpio_1 test_gpio_1 fast_uar t _tx uart_dbg _rx ? bsc _sda rf_disable_l gci_g- pio_5 ??pwdog _gpio_1 wl_dev_wake/ hsic_host_rd y gpio_2 test_gpio_2 fast_uar t _cts_in ? ? n/a tck gci_g- pio_1 ???? gpio_3 test_gpio_3 fast_uar t _rts_out ? ? n/a tms gci_g- pio_0 ???? gpio_4 test_gpio_4 uart_rx uart_dbg _rx ? n/a tdi seci_in ? ? ? ? gpio_5 test_gpio_5 uart_tx uart_dbg _tx ? n/a tdo seci_out ? ? ? ? gpio_6 test_gpio_6 ? ? ? n/a trst_l gci_g- pio_2 seci_in ? ? ? gpio_7 test_gpio_7 fast_uar t _rts_out sflash_cs sprom_cs bsc _sda pmu_test_o gci_g- pio_3 usb_mdc/ hsic_mdc ?pwdog _gpio_2 wl_led (for wlbga) gpio_8 test_gpio_8 fast_uar t _cts_in sflash_cl k sprom_clk bsc_clk ? seci_in usb_mdio/ hsic_mdio ?? pwdog _gpio_3 ? gpio_9 test_gpio_9 fast_uar t _rx sflash_mi sprom_mi paldo _pu ? seci_out paldo_pd ? pwdog _gpio_4 ? gpio_10 test_g- pio_10 fast_uar t _tx sflash_mo sprom_mo ? ? gci_g- pio_4 ??pwdog _gpio_5 hsic_dev_rdy gpio_11 test_g- pio_11 fast_uar t_rx ??paldo _pu ?gci_g- pio_5 paldo_pd ? ? usb_vbus _present gpio_12 test_g- pio_12 fast_uar t _tx ? ? ? ? gci_g- pio_1 ???
document number: 002-14809 rev. *j page 98 of 165 cyw4354 ta b l e 2 8 defines status for all cyw4354 gpios based on the tristate test mode. gpio_13 test_g- pio_13 usbphy _scan _resetb ? ? ? ? gci_g- pio_0 ???? gpio_14 test_g- pio_14 fast_uar t _rts_out uart_dbg _rx ??? gci_g- pio_2 ???? gpio_15 test_gpio_1 5 fast_uart _cts_in uart_dbg _tx ??? gci_gpio_ 3 ???? note: 1. gpio_0 and wl_dev_wake signals are selected by using software. 2. usb_vbus_present indicates that usb30d is selected. 3. sdio_padvddio = 1 (not in straps table) is set to 3.3v by default for all packages. 4.gpio_7 can be used as wl_led in wlbga packages. 5. usb_mdx/hsic_mdx mdio is the interface of usb1.0/2.0/3.0 phy or of hsic phy (depending on the strap option). table 28. gpio status vs. test modes test mode function select status for all gpios tristate_ind 12 input disable tristate_pdn 13 pull down tristate_pup 14 pull up tristate 15 tristate table 27. gpio alternative signal functions (cont.) test mode uart sflash sprom bsc miscella- neous-0 (jtag_sel = 1) gci miscellaneous- 1 miscella- neous-2 pwdog pin names function select additional functionality 0 2 3 4 5 6 7 8 9 10
document number: 002-14809 rev. *j page 99 of 165 cyw4354 13.6 i/o states the following notations are used in table 29 on page 99 : note: where applicable, the default value is shown in bold brackets (for example, [default value] . i: input signal o: output signal i/o: input/output signal pu = pulled up pd = pulled down nopull = neither pulled up nor pulled down table 29. i/o states name i/o keeper a active mode low power state/sleep (all power present) power-down b (bt_reg_on and wl_reg_on held low) out-of-reset; before sw download (bt_reg_on high; wl_reg_on high) (wl_reg_on high and bt_reg_on low) and vddios are present power rail wl_reg_on i n i: pd pull-down can be disabled i: pd pull-down can be disabled i: pd (of 200k) i: pd (of 200k) i: pd (of 200k) ? bt_reg_on clk_req i/o y open drain or push-pull programmable active high open drain or push-pull programmable active high high-z, nopull open drain active high open drain active high bt_vddio bt_host_wake i/o y i/o: pu, pd, nopull programmable i/o: pu, pd, nopull programmable high-z, nopull i: pd i: pd bt_dev_wake bt_gpio 5 bt_gpio 4 i: floating, but input disabled bt_gpio 2, 3 i: pu i: pu bt_uart_cts i y i: nopull; pu programmable i: nopull high-z, nopull i: pu i: pu bt_uart_rts o o: nopull o: nopull bt_uart_rxd i i: pu i: nopull bt_uart_txd o o: nopull o: nopull
document number: 002-14809 rev. *j page 100 of 165 cyw4354 sdio data i/o n i/o: pu (sdio mode) i: pu (sdio mode) high-z, nopull i: pu (sdio mode) i: pu (sdio mode) vddio_sd sdio cmd sdio_clk i i: nopull i: nopull i: nopull i: nopull bt_pcm_clk i/o y i: nopull c i: nopull c high-z, nopull i: pd i: pd bt_vddio bt_pcm_in bt_pcm_out bt_pcm_sync i: floating, but input disabled bt_i2s_ws i: nopull d i: nopull d i: pd bt_i2s_clk bt_i2s_di bt_i2s_do table 29. i/o states (cont.) name i/o keeper a active mode low power state/sleep (all power present) power-down b (bt_reg_on and wl_reg_on held low) out-of-reset; before sw download (bt_reg_on high; wl_reg_on high) (wl_reg_on high and bt_reg_on low) and vddios are present power rail
document number: 002-14809 rev. *j page 101 of 165 cyw4354 gpio_0 i/o y i/o: pu, pd, nopull programmable [nopull] i/o: pu, pd, nopull programmable [nopull] high-z, nopull i: nopull i: nopull vddio gpio_1 y gpio_2 y gpio_3 y gpio_4 y i/o: pu, pd, nopull programmable [pd] i/o: pu, pd, nopull programmable [pd] i: pd i: pd gpio_5 y i/o: pu, pd, nopull programmable [pd] i/o: pu, pd, nopull programmable [pd] i: pd gpio_6 y i/o: pu, pd, nopull programmable [nopull] i/o: pu, pd, nopull programmable [nopull] high-z, nopull i: nopull i: nopull gpio_7 y gpio_8 y i/o: pu, pd, nopull programmable i/o: pu, pd, nopull programmable i e i: nopull gpio_9 y i: pd gpio_10 y i/o: pu, pd, nopull programmable [pd] i/o: pu, pd, nopull programmable [pd] high-z, nopull i: pd i: pd gpio_11 y i/o: pu, pd, nopull programmable [nopull] i/o: pu, pd, nopull programmable [nopull] i: pd i: nopull i: nopull gpio_12 y i/o: pu, pd, nopull programmable [pu] i/o: pu, pd, nopull programmable [pu] high-z, nopull i: pu i: pu gpio_13 y i/o: pu, pd, nopull programmable [nopull] i/o: pu, pd, nopull programmable [nopull] i: nopull i: nopull gpio_14 y gpio_15 y rf_sw_ctrl_x i/o y o: nopull o: nopull i: pd o: nopull : nopull vddio_rf a. keeper column: n = pad has no keeper. y = pad has a keeper. keeper is always active except in power-down state. if there is n o keeper, and it is an input and there is nopull, then the pad should be driven to prevent leakage due to floating pad (sdio_clk, for example). b. in the power-down state (xx_reg_on=0): high-z; nopu ll => the pad is disabled because power is not supplied. c. depending on whether the pcm interface is enabled and the configurat ion of pcm is in master or slave mode, it can be either i nput or output. d. depending on whether the i 2 s interface is enabled and the configuration of i 2 s is in master or slave mode, it can be either input or output. e. for wlbga this gpio has nopull in this state. for wlcsp this gpio has a pu in this state. table 29. i/o states (cont.) name i/o keeper a active mode low power state/sleep (all power present) power-down b (bt_reg_on and wl_reg_on held low) out-of-reset; before sw download (bt_reg_on high; wl_reg_on high) (wl_reg_on high and bt_reg_on low) and vddios are present power rail
document number: 002-14809 rev. *j page 102 of 165 cyw4354 14. dc characteristics note : values in this data sheet are design goals and are subjec t to change based on the results of device characterization 14.1 absolute maximum ratings caution: the absolute maximum ratings in table 30 indicate levels where permanent damage to the device can occur, ev en if these limits are exceeded for only a brief duration. functional operation is not guaranteed under these conditions. operation at absolute maximu m conditions for extended periods can adversely affect long-term reliability of the device. table 30. absolute maximum ratings rating symbol value unit dc supply for vbat and pa driver supply a a. the maximum continuous voltage is 5.25v. voltage transients up to 6.0v for up to 10 seconds, cumulative duration over the lif etime of the device, are allowed. voltage transients as hi gh as 5.5v for up to 250 seconds, cumulati ve duration over the lifetime of the dev ice, are allowed. vbat ?0.5 to +6.0 v dc supply voltage for digital i/o vddio ?0.5 to 3.9 v dc supply voltage for rf switch i/os vddio_rf ?0.5 to 3.9 v dc input supply voltage for cldo and lnldo ? ?0.5 to 1.575 v dc supply voltage for rf analog vddrf ?0.5 to 1.32 v dc supply voltage for core vddc ?0.5 to 1.32 v wrf_tcxo_vdd ? ?0.5 to 3.63 v maximum undershoot voltage for i/o b b. duration not to exceed 25% of the duty cycle. v undershoot ?0.5 v maximum overshoot voltage for i/o b v overshoot vddio + 0.5 v maximum junction temperature t j 125 c
document number: 002-14809 rev. *j page 103 of 165 cyw4354 14.2 environmental ratings the environmental ratings are shown in ta b l e 3 1 . 14.3 electrostatic discharge specifications proper use of wrist and heel grounding straps is required to discharge static electricity when handling the cyw4354. caution: electrostatic discharge (esd) damage can occur if the cyw4354 is mishandled. always wear an esd-preventive wrist or heel ground strap when handling the cyw4354. as with all electrical devices of this type, take al l necessary safety precautions to prevent damage to the equipment. when not being used, always store the cyw4354 in antistatic packaging. table 31. environmental ratings characteristic value units conditions/comments ambient temperature (t a ) ?30 to +85 c functional operation a a. functionality is guaranteed but spec ifications require derating at extreme temperatures; see t he specification tables for det ails. storage temperature ?40 to +125 c ? relative humidity less than 60 % storage less than 85 % operation table 32. electrostatic discharge specifications pin type symbol condition esd rating unit esd a a. handling reference: nqy00083, section 3.4, group d9, table b. esd_hand_hbm human body model contact discharge per jedec eid/ jesd22-a114. wlbga:1.k wlcsp:1.5k v cdm esd_hand_cdm charged device model contact jedec eia/jesd22- c101. wlbga:300 wlcsp:500 v
document number: 002-14809 rev. *j page 104 of 165 cyw4354 14.4 recommended operating conditions and dc characteristics caution: functional operation is not guarantee d outside of the limits shown in table 33 , and operation outside these limits for extended periods can adversely affect long-term reliability of the device. table 33. recommended operating conditions and dc characteristics parameter symbol value unit minimum typical maximum dc supply voltage for vbat vbat 3.0 a ?5.25 b v dc supply voltage for core vdd 1.14 1.2 1.26 v dc supply voltage for rf blocks in chip vddrf 1.14 1.2 1.26 v dc supply voltage for tcxo input buffer wrf_tcxo_vdd 1.62 1.8 1.98 v dc supply voltage for digital i/o vddio, vddio_sd 1.62 ? 3.63 v dc supply voltage for rf switch i/os vddio_rf 3.13 3.3 3.46 v external tssi input tssi 0.15 ? 0.95 v internal por threshold vth_por 0.4 ? 0.7 v sdio interface i/o pins for vddio_sd = 1.8v: input high voltage vih 1.27 ? ? v input low voltage vil ? ? 0.58 v output high voltage @ 2 ma voh 1.40 ? ? v output low voltage @ 2 ma vol ? ? 0.45 v for vddio_sd = 3.3v: input high voltage vih 0.625 vddio ??v input low voltage vil ? ? 0.25 vddio v output high voltage @ 2 ma voh 0.75 vddio ??v output low voltage @ 2 ma vol ? ? 0.125 vddio v other digital i/o pins for vddio = 1.8v: input high voltage vih 0.65 vddio ??v input low voltage vil ? ? 0.35 vddio v output high voltage @ 2 ma voh vddio ? 0.45 ??v output low voltage @ 2 ma vol ? ? 0.45 v for vddio = 3.3v: input high voltage vih 2.00 ? ? v input low voltage vil ? ? 0.80 v output high voltage @ 2 ma voh vddio ? 0.4 ? ? v output low voltage @ 2 ma vol ? ? 0.40 v
document number: 002-14809 rev. *j page 105 of 165 cyw4354 rf switch control output pins c for vddio_rf = 3.3v: output high voltage @ 2 ma voh vddio ? 0.4 ? ? v output low voltage @ 2 ma vol ? ? 0.40 v input capacitance c in ??5pf a. the cyw4354 is functional across this range of voltages. opti mal rf performance specified in the data sheet, however, is guar anteed only for 3.13v < vbat < 4.8v. b. the maximum continuous voltage is 5.25v. voltage transients up to 6.0v for up to 10 seconds, cumulative duration over the lif etime of the device, are allowed. voltage transients as high as 5.5v for up to 250 seconds, cumulative duration over the lifetime of the dev ice, are allowed. c. programmable 2 ma to 16 ma drive strength. default is 10 ma. table 33. recommended operating conditions and dc characteristics (cont.) parameter symbol value unit minimum typical maximum
document number: 002-14809 rev. *j page 106 of 165 cyw4354 15. bluetooth rf specifications note: values in this data sheet are design goals and are subject to change based on the results of device characterization. unless otherwise stated, limit values ap ply for the conditions specified in table 31 on page 103 and table 33 on page 104 . typical values apply for an ambi ent temperature of +25c. figure 35. rf port location for bluetooth testing note: all bluetooth specifications are measured at the chip port unless otherwise specified. table 34. bluetooth receiver rf specifications parameter conditions minimum typical maximum unit note : the specifications in this table are measured at the chip port output un less otherwise specified. general frequency range ? 2402 ? 2480 mhz rx sensitivity gfsk, 0.1% ber, 1 mbps ? ?93.5 ? dbm ? /4?dqpsk, 0.01% ber, 2mbps ??95.5? dbm 8?dpsk, 0.01% ber, 3 mbps ? ?89.5 ? dbm input ip3 ? ?16 ? ? dbm maximum input at antenna ? ? ? ?20 dbm rx lo leakage 2.4 ghz band ? ? ?90.0 ?80.0 dbm filter rf ? switch (0.5 ? db ? insertion ? loss) antenna ? port rf ? port wlan ? tx bt ? tx wlan/bt ? rx chip port cyw4354
document number: 002-14809 rev. *j page 107 of 165 cyw4354 interference performance a c/i co-channel gfsk, 0.1% ber ? 8 11 db c/i 1 mhz adjacent channel gfsk, 0.1% ber ? ?7 0 db c/i 2 mhz adjacent channel gfsk, 0.1% ber ? ?38 ?30 db c/i ? 3 mhz adjacent channel gfsk, 0.1% ber ? ?56 ?40 db c/i image channel gfsk, 0.1% ber ? ?31 ?9 db c/i 1 mhz adjacent to image channel gfsk, 0.1% ber ? ?46 ?20 db c/i co-channel ? /4?dqpsk, 0.1% ber ? 9 13 db c/i 1 mhz adjacent channel ? /4?dqpsk, 0.1% ber ? ?11 0 db c/i 2 mhz adjacent channel ? /4?dqpsk, 0.1% ber ? ?39 ?30 db c/i ? 3 mhz adjacent channel ? /4?dqpsk, 0.1% ber ? ?55 ?40 db c/i image channel ? /4?dqpsk, 0.1% ber ? ?23 ?7 db c/i 1 mhz adjacent to image channel ? /4?dqpsk, 0.1% ber ? ?43 ?20 db c/i co-channel 8?dpsk, 0.1% ber ? 17 21 db c/i 1 mhz adjacent cha nnel 8?dpsk, 0.1% ber ? ?4 5 db c/i 2 mhz adjacent channel 8?dpsk, 0.1% ber ? ?37 ?25 db c/i ? 3 mhz adjacent channel 8?dpsk, 0.1% ber ? ?53 ?33 db c/i image channel 8?dpsk, 0.1% ber ? ?16 0 db c/i 1 mhz adjacent to image channel 8?dpsk, 0.1% ber ? ?37 ?13 db out-of-band blocking performance (cw) 30?2000 mhz 0.1% ber ? ?10.0 ? dbm 2000?2399 mhz 0.1% ber ? ?27 ? dbm 2498?3000 mhz 0.1% ber ? ?27 ? dbm 3000 mhz?12.75 ghz 0.1% ber ? ?10.0 ? dbm out-of-band blocking performance, modulated interferer gfsk (1 mbps) b 698?716 mhz wcdma ? ?13.5 ? dbm 776?849 mhz wcdma ? ?13.8 ? dbm 824?849 mhz gsm850 ? ?13.5 ? dbm 824?849 mhz wcdma ? ?14.3 ? dbm 880?915 mhz e-gsm ? ?13.1 ? dbm 880?915 mhz wcdma ? ?13.1 ? dbm 1710?1785 mhz gsm1800 ? ?18.1 ? dbm 1710?1785 mhz wcdma ? ?17.4 ? dbm 1850?1910 mhz gsm1900 ? ?19.4 ? dbm 1850?1910 mhz wcdma ? ?18.8 ? dbm 1880?1920 mhz td-scdma ? ?19.7 ? dbm 1920?1980 mhz wcdma ? ?19.6 ? dbm 2010?2025 mhz td?scdma ? ?20.4 ? dbm table 34. bluetooth receiver rf specifications (cont.) parameter conditions minimum typical maximum unit
document number: 002-14809 rev. *j page 108 of 165 cyw4354 2500?2570 mhz wcdma ? ?20.4 ? dbm 2500?2570 mhz c band 7 ? ?30.5 ? dbm 2300?2400 mhz d band 40 ? ?34.0 ? dbm 2570?2620 mhz e band 38 ? ?30.8 ? dbm 2545?2575 mhz f xgp band ? ?29.5 ? dbm dpsk (2 mbps) b 698?716 mhz wcdma ? ?9.8 ? dbm 776?794 mhz wcdma ? ?9.7 ? dbm 824?849 mhz gsm850 ? ?10.7 ? dbm 824?849 mhz wcdma ? ?11.4 ? dbm 880?915 mhz e-gsm ? ?10.4 ? dbm 880?915 mhz wcdma ? ?10.2 ? dbm 1710?1785 mhz gsm1800 ? ?15.8 ? dbm 1710?1785 mhz wcdma ? ?15.4 ? dbm 1850?1910 mhz gsm1900 ? ?16.6 ? dbm 1850?1910 mhz wcdma ? ?16.4 ? dbm 1880?1920 mhz td-scdma ? ?17.9 ? dbm 1920?1980 mhz wcdma ? ?16.8 ? dbm 2010?2025 mhz td-scdma ? ?18.6 ? dbm 2500?2570 mhz wcdma ? ?20.4 ? dbm 2500?2570 mhz c band 7 ? ?31.9 ? dbm 2300?2400 mhz d band 40 ? ?35.3 ? dbm 2570?2620 mhz e band 38 ? ?31.8 ? dbm 2545?2575 mhz f xgp band ? ?31.1 ? dbm 8dpsk (3 mbps) b 698?716 mhz wcdma ? ?12.6 ? dbm 776?794 mhz wcdma ? ?12.6 ? dbm 824?849 mhz gsm850 ? ?12.7 ? dbm 824?849 mhz wcdma ? ?13.7 ? dbm 880?915 mhz e-gsm ? ?12.8 ? dbm 880?915 mhz wcdma ? ?12.6 ? dbm 1710?1785 mhz gsm1800 ? ?18.1 ? dbm 1710?1785 mhz wcdma ? ?17.4 ? dbm 1850?1910 mhz gsm1900 ? ?19.1 ? dbm 1850?1910 mhz wcdma ? ?18.6 ? dbm 1880?1920 mhz td-scdma ? ?19.3 ? dbm 1920?1980 mhz wcdma ? ?18.9 ? dbm 2010?2025 mhz td-scdma ? ?20.4 ? dbm 2500?2570 mhz wcdma ? ?21.4 ? dbm table 34. bluetooth receiver rf specifications (cont.) parameter conditions minimum typical maximum unit /4
document number: 002-14809 rev. *j page 109 of 165 cyw4354 2500?2570 mhz c band 7 ? ?31.0 ? dbm 2300?2400 mhz d band 40 ? ?34.5 ? dbm 2570?2620 mhz e band 38 ? ?31.2 ? dbm 2545?2575 mhz f xgp band ? ?30.0 ? dbm spurious emissions 30 mhz?1 ghz ? ?95 ?62 dbm 1?12.75 ghz ? ?70 ?47 dbm 851?894 mhz ? ?147 ? dbm/hz 925?960 mhz ? ?147 ? dbm/hz 1805?1880 mhz ? ?147 ? dbm/hz 1930?1990 mhz ? ?147 ? dbm/hz 2110?2170 mhz ? ?147 ? dbm/hz a. the maximum value represents the actual bluetooth specificat ion required for bluetooth qualification as defined in the versio n4.1 specification. b. bluetooth reference level for the wanted signal at the bluetooth chip port = at 3 db desense for each data rate. c. interferer: 2560 mhz, bw=10 mhz; measured at 2480 mhz. d. interferer: 2360 mhz, bw=10 mhz; measured at 2402 mhz. e. interferer: 2380 mhz, bw=10 mhz; measured at 2480 mhz. f. interferer: 2355 mhz, bw=10 mhz; measured at 2480 mhz. table 34. bluetooth receiver rf specifications (cont.) parameter conditions minimum typical maximum unit
document number: 002-14809 rev. *j page 110 of 165 cyw4354 table 35. bluetooth transmitter rf specifications parameter conditions minimum typical maximum unit note: the specifications in this table are measured at the chip port output unless otherwise specified. general frequency range 2402 ? 2480 mhz basic rate (gfsk) tx power at bluetooth ? 13.0 ? dbm qpsk tx power at bluetooth ? 10.0 ? dbm 8psk tx power at bluetooth ? 10.0 ? dbm power control step ? 2 4 8 db note: output power is with tca and tssi enabled. gfsk in-band spurious emissions ?20 dbc bw ? ? 0.93 1 mhz edr in-band spurious emissions 1.0 mhz < |m ? n| < 1.5 mhz m ? n = the frequency range for which the spurious emission is measured relative to the transmit center frequency. ? ?38 ?26.0 dbc 1.5 mhz < |m ? n| < 2.5 mhz ? ?31 ?20.0 dbm |m ? n| ? 2.5 mhz a ? ?43 ?40.0 dbm out-of-band spurious emissions 30 mhz to 1 ghz ? ? ? ?36.0 b,c dbm 1 ghz to 12.75 ghz ? ? ? ?30.0 b,d,e dbm 1.8 ghz to 1.9 ghz ? ? ? ?47.0 dbm 5.15 ghz to 5.3 ghz ? ? ? ?47.0 dbm gps band spurious emissions spurious emissions ? ? ?103 ? dbm out-of-band noise floor f 65?108 mhz fm rx ? ?147 ? dbm/hz 776?794 mhz cdma2000 ? ?147 ? dbm/hz 869?960 mhz cdmaone, gsm850 ? ?147 ? dbm/hz 925?960 mhz e-gsm ? ?147 ? dbm/hz 1570?1580 mhz gps ? ?146 ? dbm/hz 1805?1880 mhz gsm1800 ? ?145 ? dbm/hz 1930?1990 mhz gsm1900, cdmaone, wcdma ? ?144 ? dbm/hz 2110?2170 mhz wcdma ? ?141 ? dbm/hz 2500?2570 mhz band 7 ? ?140 ? dbm 2300?2400 mhz band 40 ? ?140 ? dbm 2570?2620 mhz band 38 ? ?140 ? dbm 2545?2575 mhz xgp band ? ?140 ? dbm a. the typical number is measured at 3 mhz offset. b. the maximum value represents the value required for bluetoot h qualification as defined in the v4.1 specification. c. the spurious emissions during idle mode are the same as specified in table 35 on page 110 . d. specified at the bluetooth antenna port. e. meets this specification using a front?end band?pass filter. f. transmitted power in cellular and fm bands at the bluetooth antenna port. see figure 35 on page 106 for location of the port.
document number: 002-14809 rev. *j page 111 of 165 cyw4354 table 36. local oscillator performance parameter minimum typical maximum unit lo performance lock time ? 72 ? ? s initial carrier frequency tolerance ? 25 75 khz frequency drift dh1 packet ? 8 25 khz dh3 packet ? 8 40 khz dh5 packet ? 8 40 khz drift rate ? 5 20 khz/50 s frequency deviation 00001111 sequence in payload a a. this pattern represents an average deviation in payload. 140 155 175 khz 10101010 sequence in payload b b. pattern represents the maximum deviation in payload for 99.9% of all frequency deviations. 115 140 ? khz channel spacing ?1?mhz table 37. ble rf specifications parameter conditions minimum typical maximum unit frequency range ? 2402 ? 2480 mhz rx sense a a. dirty tx is on. gfsk, 0.1% ber, 1 mbps ? ?95.5 ? dbm tx power b b. ble tx power can be increased to compensate for front-end losses such as bpf, diplexer, switch, etc.). the output is capped a t 12 dbm out. the ble tx power at the antenna port cannot exceed the 10 dbm specification limit. ? ? 8.5 ? dbm mod char: delta f1 average ? 225 255 275 khz mod char: delta f2 max. c c. at least 99.9% of all delta f2 max. frequency val ues recorded over 10 packets must be greater than 185 khz. ? 99.9??% mod char: ratio ? 0.8 0.95 ? %
document number: 002-14809 rev. *j page 112 of 165 cyw4354 16. fm receiver specifications note : values in this data sheet are design goals and are subject to change based on the results of device characterization. unless otherwise stated, limit values ap ply for the conditions specified in table 31 on page 103 and table 33 on page 104 . typical values apply for an am bient temperature +25c. table 38. fm receiver specifications parameter conditions a minimum typical maximum units rf parameters operating frequency b frequencies inclusive 65 ? 108 mhz sensitivity c fm only snr 26 db ? 0 ? dbv emf ? 1 ? v emf ??6? dbuv receiver adjacent channel selectivity c,d measured for 30 db snr at the audio output. wanted signal: 23 dbv emf (14.1 v emf), at 200 khz. ?51? db at 400 khz ? 62 ? db intermediate signal plus noise- to-noise ratio (s+n)/n, stereo c vin = 20 dbv emf (10 v emf) 45 53 ? db intermodulation perfor- mance c,d blocker level increased until desired at 30 db snr wanted signal: 33 dbv emf (45 v emf) modulated interferer: at f wanted 400 khz and 4 mhz cw interferer: at f wanted 800 khz and 8 mhz ?55? dbc am suppression, mono c vin = 23 dbv emf (14.1 v emf) am at 400 hz with m = 0.3 no a-weighted or any other filtering applied. 40 ? ? db rds rds sensitivity e,f rds deviation = 1.2 khz ? 16 ? dbv emf ? 6.3 ? v emf ?10? dbuv rds deviation = 2 khz ? 12 ? dbv emf ? 4 ? v emf ? 6 ? dbuv rds selectivity f wanted signal: 33 dbv emf (45 v emf), 2 khz rds deviation interferer: ? f = 40 khz, fmod = 1 khz 200 khz ? 49 ? db 300 khz ? 52 ? db 400 khz ? 52 ? db rf input impedance ? 1.5 ? ? k ? antenna tuning capacitor ? 2.5 ? 30 pf maximum input level c snr > 26 db ? ? 113 dbv emf ? ? 446 mv emf ? ? 107 dbuv
document number: 002-14809 rev. *j page 113 of 165 cyw4354 rf conducted emissions (measured into a 50 ? load) local oscillator breakthrough measured on the reference port ? ? ?55 dbm 869?894 mhz, 925?960 mhz, 1805?1880 mhz, 1930?1990 mhz. gps ? ? ?90 dbm rf blocking levels at the fm antenna input 40 db snr (assumes a 50 ? at the radio input and excludes spurs) gsm850, e-gsm (std), bw = 0.2 mhz, 824?849 mhz 880?915 mhz ?7 ?dbm gsm850, e-gsm (edge), bw = 0.2 mhz, 824?849 mhz 880?915 mhz ??1 ?dbm gsm dcs 1800, pcs 1900 (std/edge), bw = 0.2 mhz, 1710?1785 mhz 1850?1910 mhz ?12 ?dbm wcdma: ii(i), iii(iv, x), bw = 5 mhz, 1850?1980 mhz (1920?1980 mhz), 1710?1785 mhz (1710?1755 mhz, 1710? 1770 mhz) ?12 ?dbm wcdma: v(vi), viii, xii, xiii, xiv, bw = 5 mhz, 824?849 mhz (830?840 mhz), 880?915 mhz ?5 ?dbm cdma2000, cdmaone, bw = 1.25 mhz, 824?849 mhz, 887?925 mhz, 776?794 mhz ?0 ?dbm cdma2000, cdmaone, bw = 1.25 mhz, 1850?1910 mhz, 1750?1780 mhz, 1920?1980 mhz ?12 ?dbm bluetooth, bw = 1 mhz, 2402?2480 mhz ?11 ?dbm ieee 802.11g/b, bw = 20 mhz, 2400?2483.5 mhz ?11 ?dbm ieee 802.11a, bw = 20 mhz, 4915?5825 mhz ?6 ?dbm 2500?2570 mhz band 7 ? 11 ? dbm 2300?2400 mhz band 40 ? 11 ? dbm 2570?2620 mhz band 38 ? 11 ? dbm 2545?2575 mhz xgp band ? 11 ? dbm tuning frequency step ? 10 ? ? khz settling time single-frequency sw itch in any direction to a frequency within the bands 88?108 mhz or 76? 90 mhz. time measured to within 5 khz of the final frequency. ?150? s search time total time for an au tomatic search to sweep from 88?108 mhz or 76?90 mhz (and reverse direction) assuming no channels are found. ??8 sec table 38. fm receiver specifications (cont.) parameter conditions a minimum typical maximum units
document number: 002-14809 rev. *j page 114 of 165 cyw4354 general audio audio output level g ? ?14.5 ? ?12.5 dbfs maximum audio output level h ???0dbfs audio dac output level g ? 72 ? 88 mv rms maximum dac audio output level h ? ? 333 ? mv rms audio dac output level difference i ??1?1db left and right ac mute fm input signal fully muted with dac enabled 60 ? ? db left and right hard mute fm input signal fully muted with dac disabled 80 ? ? db soft mute attenuation and start level muting is performed dynamically proportional to the fm wanted input signal c/n. the muting characteristic is fully programmable. refer to ?audio features? on page 45 for further details. ??? ? maximum signal plus noise-to- noise ratio (s + n)/n, mono i ??69?db maximum signal plus noise-to- noise ratio (s + n)/n, stereo g ??64?db total harmonic distortion, mono vin = 66 dbv emf (2 mv emf), ? f = 75 khz, fmod = 400 hz ??0.8% ? f = 75 khz, fmod = 1 khz ? ? 0.8 % ? f = 75 khz, fmod = 3 khz ? ? 0.8 % ? f = 100 khz, fmod = 1 khz ? ? 1.0 % total harmonic distortion, stereo vin = 66 dbv emf (2 mv emf) ? f = 67.5 khz, fmod = 1 khz, ? f pilot = 7.5 khz, l = r ??1.5% audio spurious products i range from 300 hz to 15 khz, with respect to 1 khz tone ? ? ?60 dbc audio bandwidth, upper (?3 db point) vin = 66 dbv emf (2 mv emf) ? f = 8 khz, for 50 s 15 ? ? khz audio bandwidth, lower (?3 db point) ??20hz audio in-band ripple 100 hz to 13 khz, vin = 66 dbv emf (2 mv emf) ? f = 8 khz, for 50 s ?0.5 ? 0.5 db de-emphasis time constant tolerance with respect to 50 and 75 s ? ? 5 % rssi range with 1 db resolution and 5 db accuracy at room temp 3 ? 83 dbv emf 1.41 ? 14.1m v emf ?3 ? 77 dbuv stereo decoder stereo channel separation forced stereo mode vin = 66 dbv emf (2 mv emf), ? f = 67.5 khz, fmod = 1 khz, ? f pilot = 6.75 khz r = 0, l = 1 ?48? db table 38. fm receiver specifications (cont.) parameter conditions a minimum typical maximum units
document number: 002-14809 rev. *j page 115 of 165 cyw4354 mono stereo blend and switching blending and switching is dynamically proportional to the fm wanted input signal c/n. the blending and switching characteristics are fully programmable. refer to ?audio features? on page 45 for further details. pilot suppression vin = 66 dbv emf (2 mv emf), ? f = 75 khz, fmod = 1 khz 46 ? ? db pause detection audio level at which a pause is detected relative to 1 khz tone, ? f = 22.5 khz ? ? ? ? four values in 3 db steps ?21 ? ?12 db audio pause duration four values 20 ? 40 ms a. following conditions are applied to all relevant tests unless otherwise indicated: pre-emphasis and de-emphasis of 50 us, r = l for mono, dac load 20 k ? , baf = 300 hz to 15 khz, and a-weighted filtering applied. b. contact broadcom regarding applicati ons that operate between 65 and 76 mhz. c. wanted signal: ? f = 22.5 khz, and fmod = 1 khz. d. interferer: ? f = 22.5 khz, and fmod = 1 khz. e. rds sensitivity numbers are for 87.5?108 mhz only. f. vin = ? f = 32 khz, fmod = 1 khz, ? f pilot = 7.5 khz, and 95% of blocks decoded with no errors after correction. g. vin = 66 dbv emf (2 mv emf), ? f = 22.5 khz, fmod = 1 khz, and ? f pilot = 6.75 khz. h. vin = 66 dbv emf (2 mv emf), ? f = 100 khz, fmod = 1 khz, and ? f pilot = 6.75 khz. i. vin = 66 dbv emf (2 mv emf), ? f = 22.5 khz, and fmod = 1 khz. table 38. fm receiver specifications (cont.) parameter conditions a minimum typical maximum units
document number: 002-14809 rev. *j page 116 of 165 cyw4354 17. wlan rf specifications 17.1 introduction the cyw4354 includes an integrated dual-band direct conversion r adio that supports the 2.4 ghz an d the 5 ghz bands. this section describes the rf characteristics of the 2.4 ghz and 5 ghz radios. note : values in this section of the data sheet are design goals a nd are subject to change based on the results of device characteri - zation. unless otherwise stated, limit values ap ply for the conditions specified in table 31 on page 103 and table 33 on page 104 . typical values apply for an am bient temperature +25c. figure 36. port locations (applies to 2.4 ghz and 5 ghz) 17.2 2.4 ghz band general rf specifications table 39. 2.4 ghz band general rf specifications item condition minimum typical maximum unit tx/rx switch time including tx ramp down ? ? 5 s rx/tx switch time including tx ramp up ? ? 2 s power-up and power-down ramp time dsss/cck modulations ? ? < 2 s filter rf ? switch (0.5 ? db ? insertion ? loss) antenna ? port rf ? port wlan ? tx bt ? tx wlan/bt ? rx chip port cyw4354
document number: 002-14809 rev. *j page 117 of 165 cyw4354 17.3 wlan 2.4 ghz receiver performance specifications note: the values in ta b l e 4 0 are specified at the rf port unless otherwise noted. table 40. wlan 2.4 ghz receiver performance specifications parameter condition/notes min. typ. max. unit frequency range ? 2400 ? 2500 mhz rx sensitivity ieee 802.11b a 1 mbps dsss ? ?96.4 ? dbm 2 mbps dsss ? ?94.5 ? dbm 5.5 mbps dsss ? ?91.7 ? dbm 11 mbps dsss ? ?89.4 ? dbm siso rx sensitivity ieee 802.11g (10% per for 1024 octet psdu) a 6 mbps ofdm ? ?93.5 ? dbm 9 mbps ofdm ? ?92.1 ? dbm 12 mbps ofdm ? ?91.2 ? dbm 18 mbps ofdm ? ?88.6 ? dbm 24 mbps ofdm ? ?85.3 ? dbm 36 mbps ofdm ? ?82 ? dbm 48 mbps ofdm ? ?77.3 ? dbm 54 mbps ofdm ? ?75.8 ? dbm mimo rx sensitivity ieee 802.11g (10% per for 1024 octet psdu) a 6 mbps ofdm ? ?94.5 ? dbm/core 9 mbps ofdm ? ?94 ? dbm/core 12 mbps ofdm ? ?93.2 ? dbm/core 18 mbps ofdm ? ?91.6 ? dbm/core 24 mbps ofdm ? ?88.3 ? dbm/core 36 mbps ofdm ? ?85 ? dbm/core 48 mbps ofdm ? ?80.3 ? dbm/core 54 mbps ofdm ? ?78.8 ? dbm/core siso rx sensitivity ieee 802.11n (10% per for 4096 octet psdu) a,b defined for default parameters: gf, 800 ns gi, and non?stbc. 20 mhz channel spacing for all mcs rates mcs0 ? ?93 ? dbm mcs1 ? ?90.7 ? dbm mcs2 ? ?88.2 ? dbm mcs3 ? ?85.1 ? dbm mcs4 ? ?81.5 ? dbm mcs5 ? ?76.9 ? dbm mcs6 ? ?75.3 ? dbm mcs7 ? ?73.7 ? dbm
document number: 002-14809 rev. *j page 118 of 165 cyw4354 mimo rx sensitivity ieee 802.11n (10% per for 4096 octet psdu) a,b defined for default parameters: gf, 800 ns gi, and non?stbc. 20 mhz channel spacing for all mcs rates mcs0 ? ?94.5 ? dbm/core mcs1 ? ?93.7 ? dbm/core mcs2 ? ?91.2 ? dbm/core mcs3 ? ?88.1 ? dbm/core mcs4 ? ?84.5 ? dbm/core mcs5 ? ?79.9 ? dbm/core mcs6 ? ?78.3 ? dbm/core mcs7 ? ?76.7 ? dbm/core mcs8 ? ?93 ? dbm/core mcs15 ? ?73.7 ? dbm/core siso rx sensitivity ieee 802.11n (10% per for 4096 octet psdu) a,b defined for default parameters: gf, 800 ns gi, and non?stbc. 40 mhz channel spacing for all mcs rates mcs0 ? ?90.8 ? dbm mcs1 ? ?87.9 ? dbm mcs2 ? ?85.5 ? dbm mcs3 ? ?82 ? dbm mcs4 ? ?78.9 ? dbm mcs5 ? ?74.2 ? dbm mcs6 ? ?72.7 ? dbm mcs7 ? ?71.3 ? dbm mimo rx sensitivity ieee 802.11n (10% per for 4096 octet psdu) a,b defined for default parameters: gf, 800 ns gi, and non?stbc. 40 mhz channel spacing for all mcs rates mcs0 ? ?92.3 ? dbm/core mcs1 ? ?90.9 ? dbm/core mcs2 ? ?88.5 ? dbm/core mcs3 ? ?85 ? dbm/core mcs4 ? ?81.9 ? dbm/core mcs5 ? ?77.2 ? dbm/core mcs6 ? ?75.7 ? dbm/core mcs7 ? ?74.3 ? dbm/core mcs8 ? ?90.8 ? dbm/core mcs15 ? ?71.3 ? dbm/core table 40. wlan 2.4 ghz receiver performance specifications (cont.) parameter condition/notes min. typ. max. unit
document number: 002-14809 rev. *j page 119 of 165 cyw4354 siso rx sensitivity ieee 802.11ac (10% per for 4096 octet psdu) a,b defined for default parameters: gf, 800 ns gi, and non?stbc 20 mhz channel spacing for all mcs rates mcs0, nss 1 ? ?92.3 ? dbm mcs1, nss 1 ? ?89.9 ? dbm mcs2, nss 1 ? ?88.1 ? dbm mcs3, nss 1 ? ?84.9 ? dbm mcs4, nss 1 ? ?81.4 ? dbm mcs5, nss 1 ? ?76.9 ? dbm mcs6, nss 1 ? ?75.3 ? dbm mcs7, nss 1 ? ?73.6 ? dbm mcs8, nss 1 ? ?69.2 ? dbm mimo rx sensitivity ieee 802.11ac (10% per for 4096 octet psdu) a,b defined for default parameters: gf, 800 ns gi, and non?stbc 20 mhz channel spacing for all mcs rates mcs0, nss 1 ? ?93.8 ? dbm/core mcs1, nss 1 ? ?92.9 ? dbm/core mcs2, nss 1 ? ?91.1 ? dbm/core mcs3, nss 1 ? ?87.9 ? dbm/core mcs4, nss 1 ? ?84.4 ? dbm/core mcs5, nss 1 ? ?79.9 ? dbm/core mcs6, nss 1 ? ?78.3 ? dbm/core mcs7, nss 1 ? ?76.6 ? dbm/core mcs8, nss 1 ? ?72.2 ? dbm/core mcs0, nss 2 ? ?92 ? dbm/core mcs8, nss 2 ? ?68.1 ? dbm/core siso rx sensitivity ieee 802.11ac (10% per for 4096 octet psdu) a,b defined for default parameters: gf, 800 ns gi, and non?stbc. 40 mhz channel spacing for all mcs rates mcs0, nss 1 ? ?89.5 ? dbm mcs1, nss 1 ? ?87 ? dbm mcs2, nss 1 ? ?85.2 ? dbm mcs3, nss 1 ? ?82 ? dbm mcs4, nss 1 ? ?78.8 ? dbm mcs5, nss 1 ? ?74.3 ? dbm mcs6, nss 1 ? ?72.7 ? dbm mcs7, nss 1 ? ?71.3 ? dbm mcs8, nss 1 ? ?66.9 ? dbm mcs9, nss 1 ? ?65.6 ? dbm table 40. wlan 2.4 ghz receiver performance specifications (cont.) parameter condition/notes min. typ. max. unit
document number: 002-14809 rev. *j page 120 of 165 cyw4354 mimo rx sensitivity ieee 802.11ac (10% per for 4096 octet psdu) a,b defined for default parameters: gf, 800 ns gi, and non?stbc. 40 mhz channel spacing for all mcs rates mcs0, nss 1 ? ?91 ? dbm/core mcs1, nss 1 ? ?90 ? dbm/core mcs2, nss 1 ? ?88.2 ? dbm/core mcs3, nss 1 ? ?85 ? dbm/core mcs4, nss 1 ? ?81.8 ? dbm/core mcs5, nss 1 ? ?77.3 ? dbm/core mcs6, nss 1 ? ?75.7 ? dbm/core mcs7, nss 1 ? ?74.3 ? dbm/core mcs8, nss 1 ? ?69.9 ? dbm/core mcs9, nss 1 ? ?68.6 ? dbm/core mcs0, nss 2 ? ?89 ? dbm/core mcs9, nss 2 ? ?64.2 ? dbm/core siso rx sensitivity ieee 802.11ac 20/40/80 mhz channel spacing with ldpc (10% per for 4096 octet psdu) a,b at wlan rf port. defined for default parameters: gf, 800 ns gi, ldpc coding, and non?stbc. mcs7, nss 1 20 mhz ? ?75.4 ? dbm mcs8, nss 1 20 mhz ? ?72.7 ? dbm mcs9, nss 1 20 mhz ? ?69.4 ? dbm mcs7, nss 1 40 mhz ? ?72.8 ? dbm mcs8, nss 1 40 mhz ? ?68.5 ? dbm mcs9, nss 1 40 mhz ? ?67.3 ? dbm mimo rx sensitivity ieee 802.11ac 20/40/80 mhz channel spacing with ldpc (10% per for 4096 octet psdu) a,b at wlan rf port. defined for default parameters: gf, 800 ns gi, ldpc coding, and non?stbc. mcs7, nss 2 20 mhz ? ?74 ? dbm/core mcs8, nss 2 20 mhz ? ?71.2 ? dbm/core mcs9, nss 2 20 mhz ? ?68.0 ? dbm/core mcs7, nss 2 40 mhz ? ?71.8 ? dbm/core mcs8, nss 2 40 mhz ? ?67 ? dbm/core mcs9, nss 2 40 mhz ? ?65.5 ? dbm/core blocking level for 3db rx sensi- tivity degradation (without external filtering) c 776?794 mhz cdma2000 ?8 ?24 ? dbm 824?849 mhz d cdmaone ?24.5 ?25 ? dbm 824?849 mhz d gsm850 ?16.5 ?15 ? dbm 880?915 mhz e?gsm ?2 ?16 ? dbm 1710?1785 mhz gsm1800 ?17 ?18 ? dbm 1850?1910 mhz gsm1800 ?21 ?19 ? dbm 1850?1910 mhz cdmaone ?32 ?26 ? dbm 1850?1910 mhz wcdma ?29 ?26 ? dbm 1920?1980 mhz wcdma ?32 ?28.5 ? dbm 2500?2570 mhz band 7 ?45 ?45 ? dbm 2300?2400 mhz band 40 ?50 ?50 ? dbm 2570-2620 mhz band 38 ?45 ?45 ? dbm 2545-2575 mhz xgp band ?45 ?45 ? dbm table 40. wlan 2.4 ghz receiver performance specifications (cont.) parameter condition/notes min. typ. max. unit
document number: 002-14809 rev. *j page 121 of 165 cyw4354 in-band static cw jammer immunity (fc ? 8 mhz < fcw < + 8 mhz) rx per < 1%, 54 mbps ofdm, 1000 octet psdu for: (rxsense + 23 db < rxlevel < max. input level) ?80 ? ? dbm input in?band ip3 maximum lna gain ? ?15.5 ? dbm minimum lna gain ? ?1.5 ? dbm maximum receive level @ 2.4 ghz @ 1, 2 mbps (8% per, 1024 octets) ?3.5 ? ? dbm @ 5.5, 11 mbps (8% per, 1024 octets) ?9.5 ? ? dbm @ 6?54 mbps (10% per, 1024 octets) ?9.5 ? ? dbm @ mcs0?7 rates (10% per, 4095 octets) ?9.5 ? ? dbm @ mcs8?9 rates (10% per, 4095 octets) ?11.5 ? ? dbm lpf 3 db bandwidth ? 9 ? 36 mhz adjacent channel rejection? dsss (difference between interfering and desired signal at 8% per for 1024 octet psdu with desired signal level as specified in condition/notes) desired and interfering signal 30 mhz apart 1 mbps dsss ?74 dbm 35 ? ? db 2 mbps dsss ?74 dbm 35 ? ? db desired and interfering signal 25 mhz apart 5.5 mbps dsss ?70 dbm 35 ? ? db 11 mbps dsss ?70 dbm 35 ? ? db adjacent channel rejection? ofdm (difference between interfering and desired signal (25 mhz apart) at 10% per for 1024 octet psdu with desired signal level as specified in condition/notes) 6 mbps ofdm ?79 dbm 16 ? ? db 9 mbps ofdm ?78 dbm 15 ? ? db 12 mbps ofdm ?76 dbm 13 ? ? db 18 mbps ofdm ?74 dbm 11 ? ? db 24 mbps ofdm ?71 dbm 8 ? ? db 36 mbps ofdm ?67 dbm 4 ? ? db 48 mbps ofdm ?63 dbm 0 ? ? db 54 mbps ofdm ?62 dbm ?1 ? ? db adjacent channel rejection mcs0?9 (difference between interfering and desired signal (25 mhz apart) at 10% per for 4096 octet psdu with desired signal level as specified in condition/ notes) mcs0 ?79 dbm 16 ? ? db mcs1 ?76 dbm 13 ? ? db mcs2 ?74 dbm 11 ? ? db mcs3 ?71 dbm 8 ? ? db mcs4 ?67 dbm 4 ? ? db mcs5 ?63 dbm 0 ? ? db mcs6 ?62 dbm ?1 ? ? db mcs7 ?61 dbm ?2 ? ? db mcs8 ?59 dbm ?4 ? ? db mcs9 ?57 dbm ?6 ? ? db table 40. wlan 2.4 ghz receiver performance specifications (cont.) parameter condition/notes min. typ. max. unit
document number: 002-14809 rev. *j page 122 of 165 cyw4354 ieee 802.11ac adjacent channel rejection mcs0?9 (difference between interfering and desired signal at 10% per for 4096 octet psdu with desired signal level as specified in condition/notes) mcs0 ?82 dbm ? ? ? db mcs1 ?80 dbm ? ? ? db mcs2 ?77 dbm ? ? ? db mcs3 ?74 dbm ? ? ? db mcs4 ?70 dbm ? ? ? db mcs5 ?66 dbm ? ? ? db mcs6 ?65 dbm ? ? ? db mcs7 ?64 dbm ? ? ? db mcs8 ?59 dbm ? ? ? db mcs9 ?57 dbm ? ? ? db maximum receiver gain ? ? ? 95 ? db gain control step ? ? ? 3 ? db rssi accuracy e range ?90 dbm to ?30 dbm ?5 ? 5 db range above ?30 dbm ?8 ? 8 db return loss zo = 50 ? , across the dynamic range 10 11.5 13 db receiver cascaded noise figure at maximum gain ? 4 ? db general spurs 1?18 ghz ? ? ? ?60 dbm/mhz a. derate by 1.5 db for 55c to 70c. b. sensitivity degradations for alte rnate settings in mcs modes. mm: 0.5 db drop, and sgi: 2 db drop. c. the cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that b and for the purpose of this test. it is not intended to indicate any s pecific usage of each band in any specific country. d. the blocking levels are valid for channels 1 to 11. (for hi gher channels, the performance may be lower due to third harmonic signals (3 824 mhz) falling within band.) e. the minimum and maximum values s hown have a 95% confidence level. table 40. wlan 2.4 ghz receiver performance specifications (cont.) parameter condition/notes min. typ. max. unit
document number: 002-14809 rev. *j page 123 of 165 cyw4354 17.4 wlan 2.4 ghz transmitter performance specifications note : the values in ta b l e 4 1 are specified at the rf port unless otherwise noted. table 41. wlan 2.4 ghz transmitter performance specifications parameter condition/notes min. typ. max. unit frequency range transmitted power in cellular and fm bands at 18 dbm, 100% duty cycle, 1 mbps cck a ? 2400 ? 2500 mhz 76-108 mhz fm rx ? ?149 ? dbm/hz 776-794 mhz ? ?162 ? dbm/hz 869-960 mhz cdmaone, gsm850 ??162? dbm/hz 925-960 mhz e-gsm ? ?162 ? dbm/hz 1570-1580 mhz gps ? ?152 ? dbm/hz 1805-1880 mhz gsm1800 ? -142 ? dbm/hz 1930-1990 mhz gsm1900, cdmaone, cdmaone ??143? dbm/hz 2110-2170 mhz wcdma ? ?128 ? dbm/hz 2500-2570 mhz band 7 ? ?92 ? dbm/hz 2300-2400 mhz band 40 ? ?95 ? dbm/hz 2570-2620 mhz band 38 ? ?110 ? dbm/hz 2545-2575 mhz xgp band ? ?110 ? dbm/hz harmonic level (at 18 dbm with 100% duty cycle) 4.8-5.0 ghz 2 nd harmonic ? ?18 ? dbm/hz 7.2-7.5 ghz 3 rd harmonic ? ?20 ? dbm/hz general spurs (at 18 dbm with 100% duty cycle) 1?18 ghz ? ? ? ?60 dbm/mhz ? evm does not exceed tx power at rf port for highest power level setting at 25c with spectral mask and evm compliance b 802.11b (dsss/cck) ?9 db 18 19.5 ? dbm ofdm, bpsk ?8 db 18 19 ? dbm ofdm, qpsk ?13 db 18 19 ? dbm ofdm, 16-qam ?19 db 16.5 18 ? dbm ofdm, 64-qam (r = 3/4) ?25 db 15.5 17 ? dbm ofdm, 64-qam (r = 5/6) ?28 db 14.5 16 ? dbm ofdm, 256-qam (r = 3/4, vht20) ?30 db 13.5 15 ? dbm ofdm, 256-qam (r = 5/6, vht20) ?32 db 12 13.5 ? dbm phase noise 37.4 mhz crystal, integrated from 10 khz to 10 mhz ? 0.45 ? degrees tx power control dynamic range ? 10 ? ? db closed-loop tx power variation at highest power level setting across full temperature and voltage range. applies across 10 dbm to 20 dbm output power range. ??1.5 db carrier suppression ? 15 ? ? dbc
document number: 002-14809 rev. *j page 124 of 165 cyw4354 17.5 wlan 5 ghz receiver performance specifications note : the values in table 42 on page 124 are specified at the rf port unless otherwise noted. gain control step ? ? 0.25 ? db return loss at chip port tx zo = 50 ? ?6? db a. the cellular standards listed only indicate the typical usages of that band in some countries: other standards may also be us ed within those bands b. derate by 1.5 db for temperatures higher than 55c, or supply voltages lower than 3.0v. derate by 3.0 db for supply voltages of lower than 2.7v, or supply voltages lower than 3. 0v at temperatures higher than 55c. table 42. wlan 5 ghz receiver performance specifications parameter condition/notes min. typ. max. unit frequency range ? 4900 ? 5845 mhz siso rx sensitivity ieee 802.11a (10% per for 1000 octet psdu) a 6 mbps ofdm ? ?92.5 ? dbm 9 mbps ofdm ? ?91.1 ? dbm 12 mbps ofdm ? ?90.2 ? dbm 18 mbps ofdm ? ?87.6 ? dbm 24 mbps ofdm ? ?84.3 ? dbm 36 mbps ofdm ? ?81 ? dbm 48 mbps ofdm ? ?76.3 ? dbm 54 mbps ofdm ? ?74.8 ? dbm mimo rx sensitivity ieee 802.11a (10% per for 1024 octet psdu) a,b 6 mbps ofdm ? ?93.5 ? dbm/core 9 mbps ofdm ? ?93 ? dbm/core 12 mbps ofdm ? ?92.2 ? dbm/core 18 mbps ofdm ? ?90.6 ? dbm/core 24 mbps ofdm ? ?87.3 ? dbm/core 36 mbps ofdm ? ?84 ? dbm/core 48 mbps ofdm ? ?79.3 ? dbm/core 54 mbps ofdm ? ?75.8 ? dbm/core siso rx sensitivity ieee 802.11n (10% per for 4096 octet psdu) a,b defined for default parameters: gf, 800 ns gi, and non-stbc. 20 mhz channel spacing for all mcs rates mcs0 ? ?92 ? dbm mcs1 ? ?89.7 ? dbm mcs2 ? ?87.2 ? dbm mcs3 ? ?84.1 ? dbm mcs4 ? ?80.5 ? dbm mcs5 ? ?75.9 ? dbm mcs6 ? ?74.3 ? dbm mcs7 ? ?72.7 ? dbm table 41. wlan 2.4 ghz transmitter performance specifications (cont.) parameter condition/notes min. typ. max. unit
document number: 002-14809 rev. *j page 125 of 165 cyw4354 mimo rx sensitivity ieee 802.11n (10% per for 4096 octet psdu) a,b defined for default parameters: gf, 800 ns gi, and non-stbc. 20 mhz channel spacing for all mcs rates mcs0 ? ?93.5 ? dbm/core mcs1 ? ?92.7 ? dbm/core mcs2 ? ?90.2 ? dbm/core mcs3 ? ?87.1 ? dbm/core mcs4 ? ?83.5 ? dbm/core mcs5 ? ?78.9 ? dbm/core mcs6 ? ?77.3 ? dbm/core mcs7 ? ?75.7 ? dbm/core mcs8 ? ?92 ? dbm/core mcs15 ? ?72.7 ? dbm/core siso rx sensitivity ieee 802.11n (10% per for 4096 octet psdu) a,b defined for default parameters: gf, 800 ns gi, and non-stbc. 40 mhz channel spacing for all mcs rates mcs0 ? ?89.8 ? dbm mcs1 ? ?86.9 ? dbm mcs2 ? ?84.5 ? dbm mcs3 ? ?81 ? dbm mcs4 ? ?77.9 ? dbm mcs5 ? ?73.2 ? dbm mcs6 ? ?71.7 ? dbm mcs7 ? ?70.3 ? dbm mimo rx sensitivity ieee 802.11n (10% per for 4096 octet psdu) a,b defined for default parameters: gf, 800 ns gi, and non-stbc. 40 mhz channel spacing for all mcs rates mcs0 ? ?91.3 ? dbm/core mcs1 ? ?89.9 ? dbm/core mcs2 ? ?87.5 ? dbm/core mcs3 ? ?84 ? dbm/core mcs4 ? ?80.9 ? dbm/core mcs5 ? ?76.2 ? dbm/core mcs6 ? ?74.7 ? dbm/core mcs7 ? ?73.3 ? dbm/core mcs8 ? ?89.8 ? dbm/core mcs15 ? ?70.3 ? dbm/core table 42. wlan 5 ghz receiver performance specifications (cont.) parameter condition/notes min. typ. max. unit
document number: 002-14809 rev. *j page 126 of 165 cyw4354 siso rx sensitivity ieee 802.11ac (10% per for 4096 octet psdu) a,b defined for default parameters: gf, 800 ns gi, and non-stbc 20 mhz channel spacing for all mcs rates mcs0, nss 1 ? ?91.3 ? dbm mcs1, nss 1 ? ?88.3 ? dbm mcs2, nss 1 ? ?86 ? dbm mcs3, nss 1 ? ?83 ? dbm mcs4, nss 1 ? ?79.4 ? dbm mcs5, nss 1 ? ?74.9 ? dbm mcs6, nss 1 ? ?73.3 ? dbm mcs7, nss 1 ? ?72.6 ? dbm mcs8, nss 1 ? ?68.2 ? dbm mimo rx sensitivity ieee 802.11ac (10% per for 4096 octet psdu) a,b defined for default parameters: gf, 800 ns gi, and non-stbc 20 mhz channel spacing for all mcs rates mcs0, nss 1 ? ?92.8 ? dbm/core mcs1, nss 1 ? ?91.3 ? dbm/core mcs2, nss 1 ? ?89 ? dbm/core mcs3, nss 1 ? ?86 ? dbm/core mcs4, nss 1 ? ?82.4 ? dbm/core mcs5, nss 1 ? ?77.9 ? dbm/core mcs6, nss 1 ? ?76.3 ? dbm/core mcs7, nss 1 ? ?75.6 ? dbm/core mcs8, nss 1 ? ?71.2 ? dbm/core mcs0, nss 2 ? ?91 ? dbm/core mcs8, nss 2 ? ?67.1 ? dbm/core siso rx sensitivity ieee 802.11ac (10% per for 4096 octet psdu) a,b defined for default parameters: gf, 800 ns gi, and non-stbc. 40 mhz channel spacing for all mcs rates mcs0, nss 1 ? ?88.5 ? dbm mcs1, nss 1 ? ?85.5 ? dbm mcs2, nss 1 ? ?83.7 ? dbm mcs3, nss 1 ? ?80.5 ? dbm mcs4, nss 1 ? ?77.5 ? dbm mcs5, nss 1 ? ?72.5 ? dbm mcs6, nss 1 ? ?71.7 ? dbm mcs7, nss 1 ? ?70.3 ? dbm mcs8, nss 1 ? ?65.9 ? dbm mcs9, nss 1 ? ?64.6 ? dbm table 42. wlan 5 ghz receiver performance specifications (cont.) parameter condition/notes min. typ. max. unit
document number: 002-14809 rev. *j page 127 of 165 cyw4354 mimo rx sensitivity ieee 802.11ac (10% per for 4096 octet psdu) a,b defined for default parameters: gf, 800 ns gi, and non-stbc. 40 mhz channel spacing for all mcs rates mcs0, nss 1 ? ?90 ? dbm/core mcs1, nss 1 ? ?88.5 ? dbm/core mcs2, nss 1 ? ?86.7 ? dbm/core mcs3, nss 1 ? ?83.5 ? dbm/core mcs4, nss 1 ? ?80.5 ? dbm/core mcs5, nss 1 ? ?75.5 ? dbm/core mcs6, nss 1 ? ?74.7 ? dbm/core mcs7, nss 1 ? ?73.3 ? dbm/core mcs8, nss 1 ? ?68.9 ? dbm/core mcs9, nss 1 ? ?67.6 ? dbm/core mcs0, nss 2 ? ?88 ? dbm/core mcs9, nss 2 ? ?63.2 ? dbm/core siso rx sensitivity ieee 802.11ac (10% per for 4096 octet psdu) a,b defined for default parameters: gf, 800 ns gi, and non-stbc. 80 mhz channel spacing for all mcs rates mcs0, nss 1 ? ?85 ? dbm mcs1, nss 1 ? ?82 ? dbm mcs2, nss 1 ? ?80 ? dbm mcs3, nss 1 ? ?76.7 ? dbm mcs4, nss 1 ? ?73.7 ? dbm mcs5, nss 1 ? ?70.5 ? dbm mcs6, nss 1 ? ?68 ? dbm mcs7, nss 1 ? ?66.5 ? dbm mcs8, nss 1 ? ?62.3 ? dbm mcs9, nss 1 ? ?60.5 ? dbm mimo rx sensitivity ieee 802.11ac (10% per for 4096 octet psdu) a,b defined for default parameters: gf, 800 ns gi, and non-stbc. 80 mhz channel spacing for all mcs rates mcs0, nss 1 ? ?86.5 ? dbm/core mcs1, nss 1 ? ?85 ? dbm/core mcs2, nss 1 ? ?83 ? dbm/core mcs3, nss 1 ? ?79.7 ? dbm/core mcs4, nss 1 ? ?76.7 ? dbm/core mcs5, nss 1 ? ?73.5 ? dbm/core mcs6, nss 1 ? ?71 ? dbm/core mcs7, nss 1 ? ?69.5 ? dbm/core mcs8, nss 1 ? ?65.3 ? dbm/core mcs9, nss 1 ? ?63.5 ? dbm/core mcs0, nss 2 ? ?84.3 ? dbm/core mcs9, nss 2 ? ?59.5 ? dbm/core table 42. wlan 5 ghz receiver performance specifications (cont.) parameter condition/notes min. typ. max. unit
document number: 002-14809 rev. *j page 128 of 165 cyw4354 siso rx sensitivity ieee 802.11ac 20/40/80 mhz channel spacing with ldpc (10% per for 4096 octet psdu) a,b at wlan rf port. defined for default parameters: gf, 800 ns gi, ldpc coding, and non-stbc. mcs7, nss 1 20 mhz ? ?74.4 ? dbm ? mcs8, nss 1 20 mhz ? ?71.7 ? dbm ? mcs9, nss 1 20 mhz ? ?71.4 ? dbm ? mcs7, nss 1 40 mhz ? ?71.8 ? dbm ? mcs8, nss 1 40 mhz ? ?67.5 ? dbm ? mcs9, nss 1 40 mhz ? ?66.5 ? dbm ? mcs7, nss 1 80 mhz ? ?68 ? dbm ? mcs8, nss 1 80 mhz ? ?64.3 ? dbm ? mcs9, nss 1 80 mhz ? ?62.5 ? dbm mimo rx sensitivity ieee 802.11ac 20/40/80 mhz channel spacing with ldpc (10% per for 4096 octet psdu) a,b at wlan rf port. defined for default parameters: gf, 800 ns gi, ldpc coding, and non-stbc. mcs7, nss 2 20 mhz ? ?73 ? dbm/core ? mcs8, nss 2 20 mhz ? ?70.2 ? dbm/core ? mcs9, nss 2 20 mhz ? ?66.5 ? dbm/core ? mcs7, nss 2 40 mhz ? ?70.8 ? dbm/core ? mcs8, nss 2 40 mhz ? ?66 ? dbm/core ? mcs9, nss 2 40 mhz ? ?64.7 ? dbm/core ? mcs7, nss 2 80 mhz ? ?67 ? dbm/core ? mcs8, nss 2 80 mhz ? ?62.8 ? dbm/core ? mcs9, nss 2 80 mhz ? ?60.5 ? dbm/core table 42. wlan 5 ghz receiver performance specifications (cont.) parameter condition/notes min. typ. max. unit
document number: 002-14809 rev. *j page 129 of 165 cyw4354 alternate adjacent channel rejection blocking level for 3 db rx sensitivity degradation c (without external filtering) 776?794 mhz cdma2000 ?21 ? ? dbm 824?849 mhz d cdmaone ?20 ? ? dbm 824?849 mhz d gsm850 ?12 ? ? dbm 880?915 mhz e-gsm ?12 ? ? dbm 1710?1785 mhz gsm1800 ?15 ? ? dbm 1850?1910 mhz gsm1800 ?15 ? ? dbm 1850?1910 mhz cdmaone ?20 ? ? dbm 1850?1910 mhz wcdma ?21 ? ? dbm 1920?1980 mhz wcdma ?21 ? ? dbm 2500?2570 mhz band 7 ?21 ? ? dbm 2300?2400 mhz band 40 ?21 ? ? dbm 2570?2620 mhz band 38 ?21 ? ? dbm 2545?2575 mhz xgp band ?21 ? ? dbm input in-band ip3 maximum lna gain ? ?15.5 ? dbm minimum lna gain ? ?1.5 ? dbm maximum receive level @ 5.24 ghz @ 6, 9, 12 mbps ?9.5 ? ? dbm @ 18, 24, 36, 48, 54 mbps ?14.5 ? ? dbm lpf 3 db bandwidth ? 9 ? 36 mhz adjacent channel rejection (difference between interfering and desired signal (20 mhz apart) at 10% per for 1000 octet psdu with desired signal level as specified in condition/ notes) 6 mbps ofdm ?79 dbm 16 ? ? db 9 mbps ofdm ?78 dbm 15 ? ? db 12 mbps ofdm ?76 dbm 13 ? ? db 18 mbps ofdm ?74 dbm 11 ? ? db 24 mbps ofdm ?71 dbm 8 ? ? db 36 mbps ofdm ?67 dbm 4 ? ? db 48 mbps ofdm ?63 dbm 0 ? ? db 54 mbps ofdm ?62 dbm ?1 ? ? db 65 mbps ofdm ?61 dbm ?2 ? ? db (difference between interfering and desired signal (40 mhz apart) at 10% per for 1000 e octet psdu with desired signal level as specified in condition/ notes) 6 mbps ofdm ?78.5 dbm 32 ? ? db 9 mbps ofdm ?77.5 dbm 31 ? ? db 12 mbps ofdm ?75.5 dbm 29 ? ? db 18 mbps ofdm ?73.5 dbm 27 ? ? db 24 mbps ofdm ?70.5 dbm 24 ? ? db 36 mbps ofdm ?66.5 dbm 20 ? ? db 48 mbps ofdm ?62.5 dbm 16 ? ? db 54 mbps ofdm ?61.5 dbm 15 ? ? db 65 mbps ofdm ?60.5 dbm 14 ? ? db maximum receiver gain ? ? 95 ? db gain control step ? ? 3 ? db rssi accuracy f range ?90 dbm to ?30 dbm ?5 ? 5 db range above ?30 dbm ?8 ? 8 db table 42. wlan 5 ghz receiver performance specifications (cont.) parameter condition/notes min. typ. max. unit
document number: 002-14809 rev. *j page 130 of 165 cyw4354 return loss zo = 50 ? , across the dynamic range 10 ? 13 db receiver cascaded noise figure at maximum gain ? 5 ? db general spurs 1?18 ghz ? ? ? ?65 dbm/mhz a. derate by 1.5 db for 55c to 70c. b. the cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that b and for the purpose of this test. it is not intended to indicate any s pecific usage of each band in any specific country. c. the cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that b and for the purpose of this test. it is not intended to indicate any s pecific usage of each band in any specific country. d. the blocking levels are valid for channels 1 to 11. (for hi gher channels, the performance may be lower due to third harmonic signals (3 824 mhz) falling within band.) e. for 65 mbps, the size is 4096. f. the minimum and maximum values s hown have a 95% confidence level. table 42. wlan 5 ghz receiver performance specifications (cont.) parameter condition/notes min. typ. max. unit
document number: 002-14809 rev. *j page 131 of 165 cyw4354 17.6 wlan 5 ghz transmitter performance specifications note : the values in ta b l e 4 3 are specified at the rf port unless otherwise noted. table 43. wlan 5 ghz transmitter performance specifications parameter condition/notes min. typ. max. unit frequency range ? 4900 ? 5845 mhz transmitted power in cellular and fm bands (at 18 dbm) a a. the cellular standards listed indicate only typical usages of that band in some c ountries. other standards may also be used w ithin those bands. 76-108 mhz fmrx ? ?162 ? dbm/hz 776-794 mhz ? ? ?168 ? dbm/hz 869-960 mhz cdmaone, gsm850 ? ?167 ? dbm/hz 1570-1580 mhz gps ? ?170 ? dbm/hz 1592-1610 mhz glonass ? ?162 ? dbm/hz 1805-1880 mhz gsm1800 ? ?169 ? dbm/hz 1850-1910 mhz gsm1900 ? ?169 ? dbm/hz 1910-1930 mhz band 37 ? ?168 ? dbm/hz 1930-1990 mhz gsm1900, cdmaone, wcdma ? ?168 ? dbm/hz 2010-2075 mhz tdscdma ? ?168 ? dbm/hz 2110-2170 mhz wcdma ? ?160 ? dbm/hz 2300-2370 mhz band 40 ? ?166 ? dbm/hz 2370-2400 mhz band 40 ? ?162 ? dbm/hz 2496-2530 mhz band 41 ? ?165 ? dbm/hz 2530-2560 mhz band 41 ? ?165 ? dbm/hz 2570-2690 mhz band 41 ? ?158 ? dbm/hz harmonic level (at 17 dbm) 9.8-11.570 ghz 2 nd harmonic ? ?30 ? dbm/mhz general spurs 1-18 ghz ? ? ? ?57 dbm/mhz tx power at rf port for highest power level setting at 25c with spectral mask and evm compliance b b. derate by 1.5 db for temperatures higher than 55c, or supply voltages lower than 3.0v. derate by 3.0 db for supply voltages of lower than 2.7v, or supply voltages lower than 3. 0v at temperatures higher than 55c. ofdm, qpsk ?13 db 17.5 18.5 ? dbm ofdm, 16-qam ?19 db 16 17.5 ? dbm ofdm, 64-qam ? ? ? ? (r = 3/4) ?25 db 15 16.5 ? dbm ofdm, 64-qam ? ? ? ? (r = 5/6) ?28 db 14 15.5 ? dbm ofdm, 256-qam (r = 3/4, vht) ?30 db 13 14.5 ? dbm ofdm, 256-qam (r = 5/6, vht) ?32 db 11 12.5 ? dbm phase noise 37.4 mhz crystal, integrated from 10 khz to 10 mhz ? 0.5 ? degrees tx power control dynamic range ? 10 ? ? db closed loop tx power variation at highest power level setting across full-temperature and voltage range. applies across 10 to 20 dbm output power range. ??2.0db carrier suppression ? 15 ? ? dbc gain control step ? ? 0.25 ? db return loss zo = 50 ? ?6?db
document number: 002-14809 rev. *j page 132 of 165 cyw4354 18. internal regulator electrical specifications note: values in this data sheet are design goals and are subject to change based on the results of device characterization. functional operation is not guarant eed outside of the specification limits provided in this section. 18.1 core buck switching regulator table 44. core buck switching regulator (cbuck) specifications specification notes min. typ. max. units input supply voltage (dc) dc voltage range inclusive of disturbances. 3.0 3.6 5.25 a a. the maximum continuous voltage is 5.25v. voltages up to 6.0v fo r up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. voltages as high as 5.5v for up to 250 seconds, cumula tive duration, over the lifetime of the device are allowed. v pwm mode switching frequency ccm, load > 100 ma vbat = 3.6v 2.8 4 5.2 mhz pwm output current ? ? ? 600 ma output current limit ? ? 1400 ? ma output voltage range programmable, 30 mv steps default = 1.35v 1.2 1.35 1.5 v pwm output voltage dc accuracy includes load and line regulation. forced pwm mode ?4 ? 4 % pwm ripple voltage, static measure with 20 mhz bandwidth limit. static load. max. ripple based on vbat = 3.6v, vout = 1.35v, fsw = 4 mhz, 2.2 h inductor l > 1.05 h, cap + board total-esr < 20 m ? , c out > 1.9 f, esl<200ph ?720mvpp pwm mode peak efficiency peak efficiency at 200 ma load 78 86 ? % pfm mode efficiency 10 ma load current 70 81 ? % start-up time from power down vio already on and steady. time from reg_on rising edge to cldo reaching 1.2v ? ? 850 s external inductor 0806 size, 30%, 0.11 25% ohms ? 2.2 ? h external output capacitor ceramic, x5r, 0402, esr <30 m ? at 4 mhz, 20%, 6.3v 2.0 b b. minimum capacitor value refers to the residual capacitor val ue after taking into account the part?to?part tolerance, dc?bias, temperature, and aging. 4.7 10 c c. total capacitance includes those connec ted at the far end of the active load. f external input capacitor for sr_vddbatp5v pin, ceramic, x5r, 0603, esr < 30 m ? at 4 mhz, 20%, 6.3v, 4.7 f 0.67 b 4.7 ? f input supply voltage ramp-up time 0 to 4.3v 40 ? ? s
document number: 002-14809 rev. *j page 133 of 165 cyw4354 18.2 3.3v ldo (ldo3p3) table 45. ldo3p3 specifications specification notes min. typ. max. units input supply voltage, v in min. = v o + 0.2v = 3.5v dropout voltage requirement must be met under maximum load for performance specifications. 2.3 3.6 5.25 a a. the maximum continuous voltage is 5.25v. voltages up to 6.0v fo r up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. voltages as high as 5.5v for up to 250 seconds, cumula tive duration, over the lifetime of the device are allowed. v output current ? 0.2 ? 600 ma nominal output voltage, v o default = 3.3v ? 3.3 ? v dropout voltage at max. load. ? ? 200 mv output voltage dc accuracy includes line/load regulation. ?5 ? +5 % quiescent current no load ? 100 120 a maximum load (600 ma) ? 5.8 6 ma leakage current power-down mode, junction temperature = 85c ?1.55 a line regulation v in from (v o + 0.2v) to 4.8v, max. load ? ? 3.5 mv/v load regulation load from 1 ma to 450 ma ? ? 0.25 mv/ma psrr v in v o + 0.2v, v o = 3.3v, c o = 4.7 f, max. load, 100 hz to 100 khz 20 ? ? db ldo turn-on time chip already powered up. ? 160 250 s external output capacitor, c o ceramic, x5r, 0402, (esr: 5 m ? ?240 m ? ), 10%, 10v 1.0 b b. minimum capacitor value refers to the re sidual capacitor value after taking into ac count the part-to-part tolerance, dc-bias, temperature, and aging. 4.7 ? f external input capacitor for sr_v ddbata5v pin (shared with bandgap) ceramic, x5r, 0402, (esr: 30m-200 m ? ), 10%, 10v. not needed if sharing vbat capacitor 4.7 f with sr_vddbatp5v. ?4.7? f
document number: 002-14809 rev. *j page 134 of 165 cyw4354 18.3 3.3v ldo (ldo3p3_b) table 46. ldo3p3_b specifications specification notes min. typ. max. units input supply voltage, v in min. = v o + 0.2v = 3.5v dropout voltage requirement must be met under maximu m load for performance specifications. 2.3 3.6 5.25 a a. the maximum continuous voltage is 5.25v. voltages up to 6.0v for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. voltages as high as 5.5v for up to 250 seconds, cumula tive duration, over the lifetime of the device are allowed. v output current ? 0.1 ? 150 ma nominal output voltage, v o default = 3.3v ? 3.3 ? v dropout voltage at max. load. ? ? 200 mv output voltage dc accuracy includes line/load regulation. ?5 ? +5 % quiescent current no load ? 10 16 a maximum load (150 ma) ? ? 1.38 1.4 ma leakage current power-down mode, junction temperature = 85c ?1.55 a line regulation v in from (v o + 0.2v) to 4.8v, max. load ? ? 3.5 mv/v load regulation load from 1 ma to 450 ma ? ? 0.25 mv/ma psrr v in v o + 0.2v, v o = 3.3v, c o = 4.7 f, max. load, 100 hz to 100 khz 20 ? ? db ldo turn-on time chip already powered up. ? ? 150 s external output capacitor, c o ceramic, x5r, 0402, (esr: 5 m ? ?240 m ? ), 10%, 10v 0.7 b b. minimum capacitor value refers to the residual capacitor value after taking into account the part?to?part tolerance, dc?bias, temperature, and aging. 2.2 ? f external input capacitor for sr_vddb ata5v pin (shared with bandgap) ceramic, x5r, 0402 ?4.7? f
document number: 002-14809 rev. *j page 135 of 165 cyw4354 18.4 2.5v ldo (btldo2p5) table 47. btldo2p5 specifications specification notes min. typ. max. units input supply voltage min. = 2.5v + 0.2v = 2.7v. dropout voltage requirement must be met under maximum load for performance specifi- cations. 3.0 3.6 5.25 a a. the maximum continuous voltage is 5.25v. voltages up to 6.0v fo r up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. voltages as high as 5.5v for up to 250 seconds, cumu lative duration, over the life time of the device are allowed. v nominal output voltage default = 2.5v. ? 2.5 ? v output voltage programmability range 2.2 2.5 2.8 v accuracy at any step (including line/load regulation), load > 0.1 ma. ?5 ? 5 % dropout voltage at maximum load. ? ? 200 mv output current ? 0.1 ? 70 ma quiescent current no load. ? 8 16 a maximum load at 70 ma. ? 660 700 a leakage current power-down mode. ? 1.5 5 a line regulation v in from (v o + 0.2v) to 4.8v, maximum load. ??3.5mv/v load regulation load from 1 ma to 70 ma, v in = 3.6v. ??0.3mv/ma psrr v in v o + 0.2v, v o = 2.5v, c o = 2.2 f, maximum load, 100 hz to 100 khz. 20 ? ? db ldo turn-on time chip already powered up. ? ? 150 s in-rush current v in = v o + 0.15v to 4.8v, c o = 2.2 f, no load. ??250ma external output capacitor, c o ceramic, x5r, 0402, (esr: 5?240 m ? ), 10%, 10v 0.7 b b. the minimum value refers to the residual capacitor value afte r taking into account part?to?part tolerance, dc?bias, temperatu re, and aging. 2.2 2.64 f external input capacitor for sr _vddbata5v pin (shared with bandgap) ceramic, x5r, 0402, (esr: 30?200 m ? ), 10%, 10v. not needed if sharing vbat 4.7 f capacitor with sr_vddbatp5v. ?4.7? f
document number: 002-14809 rev. *j page 136 of 165 cyw4354 18.5 cldo table 48. cldo specifications specification notes min. typ. max. units input supply voltage, v in min. = 1.2 + 0.15v = 1.35v dropout voltage requirement must be met under maximum load. 1.31.351.5 v output current ? 0.2 ? 300 ma output voltage, v o programmable in 25 mv steps. default = 1.2.v 1.1 1.2 1.275 v dropout voltage at max. load ? ? 150 mv output voltage dc accuracy includes line/load regulation ?4 ? +4 % quiescent current no load ? 24 ? a 300 ma load ? 2.1 ? ma line regulation v in from (v o + 0.15v) to 1.5v, maximum load ? ? 5 mv/v load regulation load from 1 ma to 300 ma ? 0.02 0.05 mv/ma leakage current power down ? ? 20 a bypass mode ? 1 3 a psrr @1 khz, vin 1.35v, c o = 4.7 f 20 ? ? db start-up time of pmu vio up and st eady. time from the reg_on rising edge to the cldo reaching 1.2v. ??700s ldo turn-on time ldo turn-on time when rest of the chip is up ? 140 180 s external output capacitor, c o total esr: 5 m ? ?240 m ? 1.32 a a. minimum capacitor value refers to the residual capacitor value afte r taking into account the part?to?part tolerance, dc?bias, temperature, and aging. 4.7 ? f external input capacitor only use an ex ternal input capacitor at the vdd_ldo pin if it is not supplied from cbuck output. ?12.2f
document number: 002-14809 rev. *j page 137 of 165 cyw4354 18.6 lnldo table 49. lnldo specifications specification notes min. typ. max. units input supply voltage, vin min. = 1.2v o + 0.15v = 1.35v dropout voltage requirement must be met under maximum load. 1.31.351.5 v output current ? 0.1 ? 150 ma output voltage, v o programmable in 25 mv steps. default = 1.2v 1.1 1.2 1.275 v dropout voltage at maximum load ? ? 150 mv output voltage dc accuracy include s line/load regulation ?4 ? +4 % quiescent current no load ? 44 ? a max. load ? 970 990 a line regulation v in from (v o + 0.1v) to 1.5v, max. load ? ? 5 mv/v load regulation load from 1 ma to 150 ma ? 0.02 0.05 mv/ma leakage current power-down ? ? 10 a output noise @30 khz, 60?150 ma load c o = 2.2 f @100 khz, 60?150 ma load c o = 2.2 f ? ? 60 35 nv/rt hz nv/ rt hz psrr @ 1khz, input > 1.35v, c o = 2.2 f, v o = 1.2v 20 ? ? db ldo turn-on time ldo turn-on time when rest of chip is up ? 140 180 s external output capacitor, c o total esr (trace/capacitor): 5 m ? ?240 m ? 0.5 a a. minimum capacitor value refers to the residual capacitor val ue after taking into account the part?to?part tolerance, dc?bias, temperature, and aging. 2.2 4.7 f external input capacitor only use an external input capacitor at the vdd_ldo pin if it is not supplied from cbuck output. total esr (trace/capacitor): 30 m ? ?200 m ? ? 1 2.2 f
document number: 002-14809 rev. *j page 138 of 165 cyw4354 19. system power consumption note: values in this data sheet are design goals and are subject to change based on the results of device characterization. unless otherwise stated, these values apply fo r the conditions specified in table 33: ?r ecommended operating conditions and dc characteristics,? on page 113. 19.1 wlan current consumption the wlan current consumption measurements are shown in ta b l e 5 0 . all values in ta b l e 5 0 are with the bluetooth core in rese t (that is, bluetooth and fm are off). table 50. typical wlan power consumption mode bandwidth (mhz) band (ghz) vbat = 3.6v) ma vio = 1.8v ua a sleep modes off b ? ? 0.003 5.5 sleep c ? ? 0.005 260 ieee power save, dtim 1 1 rx core d 20 2.4 1.2 260 ieee power save, dtim 3 1 rx core d 20 2.4 0.4 260 ieee power save, dtim 1 1 rx core d 20 5 1.2 260 ieee power save, dtim 3 1 rx core d 20 5 0.4 260 ieee power save, dtim 1 1 rx core d 40 5 1.5 260 ieee power save, dtim 3 1 rx core d 40 5 0.5 260 ieee power save, dtim 1 1 rx core d 80 5 2.0 260 ieee power save, dtim 3 1 rx core d 80 5 0.7 260 active modes transmit cck 1 chain e 20 2.4 350 60 mcs8, nss 1, ht20, sgi f,g,h 20 2.4 270 60 tmcs8, nss 2, ht20, sgi f,g,h 20 2.4 540 60 mcs7, sgi f, g,i 20 5 310 60 mcs15, sgi f, g,i 20 5 620 60 mcs7 f,g,i 40 5 315 60 mcs9, nss 1, sgi f,g,j 40 5 295 60 mcs9, nss 2, sgi f,g,j 40 5 590 60 mcs9, nss 1, sgi f,g,j 80 5 305 60 mcs9, nss 2, sgi f,g,j 80 5 610 60 receive 1 mbps, 1 rx core 20 2.4 59 60 1 mbps, 2 rx cores 20 2.4 75 60 mcs7, ht20 1 rx core k 20 2.4 62 60 mcs7, ht20 2 rx cores k 20 2.4 81 60 mcs15, ht20 k 20 2.4 86 60 crs 1 rx core l 20 2.4 57 60 crs 2 rx cores l 20 2.4 76 60 receive mcs7, sgi 1 rx core k 20 5 71 60
document number: 002-14809 rev. *j page 139 of 165 cyw4354 receive mcs7, sgi 2 rx cores k 20 5 102 60 receiver mcs15, sgi k 20 5 106 60 crs 1 rx core l 20 5 67 60 crs 2 rx cores l 20 5 96 60 receive mcs 7, sgi 1 rx core k 40 5 91 60 receive mcs 7, sgi 2 rx cores k 40 5 135 60 receive mcs 15, sgi k 40 5 141 60 crs 1 rx core l 40 5 80 60 crs 2 rx cores l 40 5 121 60 receive mcs9, nss 1, sgi k 80 5 123 60 receive mcs9, nss 1, sgi 2 rx cores k 80 5 189 60 receive mcs9, nss 2, sgi k 80 5 206 60 crs 1 rx core l 80 5 102 60 crs 2 rx cores l 80 5 163 60 a. specified with all pins idle (not switching) and not driving any loads. b. wl_reg_on, bt_reg_on low, no vddio. c. idle, not associated, or inter-beacon. d. beacon interval = 102.4 ms. beacon duration = 1 ms @1 mbps. average current over 3 dtim intervals. e. output power per core at rf port = 21 dbm f. duty cycle is 100% g. measured using packet engine test mode. h. output power per core at rf port = 17 dbm. i. output power per core at rf port = 17.5 dbm. j. output power per core at rf port = 14 dbm. k. duty cycle is 100%. carrier sense (cs) detect/packet receive. l. carrier sense (cca) when no carrier present. table 50. typical wlan power consumption (cont.) mode bandwidth (mhz) band (ghz) vbat = 3.6v) ma vio = 1.8v ua a
document number: 002-14809 rev. *j page 140 of 165 cyw4354 19.2 bluetooth and fm current consumption the bluetooth, ble, and fm current c onsumption measurements are shown in table 51 . note: the wlan core is in reset (wlan_reg_on = low) for all measurements provided in ta b l e 5 1 . for fm measurements, the bluetooth core is in sleep mode. the bt current consumption numbers are measur ed based on gfsk tx output power = 10 dbm. table 51. bluetooth ble and fm current consumption operating mode vbat (vbat = 3.6v) typical vddio (vddio = 1.8v) typical units sleep 13 198 a standard 1.28s inquiry scan 0.217 0.197 ma p and i scan b 440 194 a 500 ms sniff master 0.168 0.195 ma 500 ms sniff slave 0.124 0.190 ma dm1/dh1 master 25.3 0.024 ma dm3/dh3 master 30.6 0.035 ma dm5/dh5 master 31.4 0.037 ma 3dh5 master 29.2 0.094 ma sco hv3 master 11.45 0.089 ma hv3 + sniff + scan a a. at maximum class 1 tx power, 500 ms sniff, four attempts (slave), p = 1.28s, and i = 2.56s. 11.7 0.090 ma fmrx i 2 s audio 8.0 ? ma fmrx analog audio only 8.6 ? ma fmrx i 2 s audio + rds 8.0 ? ma fmrx analog audio + rds 8.6 ? ma ble scan b b. no devices present. a 1.28 second inte rval with a scan window of 11.25 ms. 244 196 a ble scan 10 ms 21.34 0.013 ma ble adv?unconnectable 1.00 sec 67 199 a ble adv?unconnectable 1.28 sec 55 199 a ble adv?unconnectable 2.00 sec 58 199 a ble connected 7. 5 ms 3.95 0.013 ma ble connected 1 sec. 57 198 a ble connected 1.28 sec. 52 197 a
document number: 002-14809 rev. *j page 141 of 165 cyw4354 20. interface timing an d ac characteristics 20.1 sdio timing 20.1.1 sdio default mode timing sdio default mode timing is shown by the combination of figure 37 and table 52 . figure 37. sdio bus timing (default mode) t wl t wh f pp t thl t isu t tlh t ih t odly (max) t odly (min) input output sdio_clk
document number: 002-14809 rev. *j page 142 of 165 cyw4354 table 52. sdio bus timing a parameters (default mode) a. timing is based on cl ? 40pf load on cmd and data. parameter symbol minimum typical maximum unit sdio clk (all values are referred to minimum vih and maximum vil b ) b. min. (vih) = 0.7 vddio and max. (vil) = 0.2 vddio. frequency ? data transfer mode fpp 0 ? 25 mhz frequency ? identification mode fod 0 ? 400 khz clock low time twl 10 ? ? ns clock high time twh 10 ? ? ns clock rise time ttlh ? ? 10 ns clock low time tthl ? ? 10 ns inputs: cmd, dat (referenced to clk) input setup time tisu 5 ? ? ns input hold time tih 5 ? ? ns outputs: cmd, dat (referenced to clk) output delay time ? data transfer mode todly 0 ? 14 ns output delay time ? iden tification mode todly 0 ? 50 ns
document number: 002-14809 rev. *j page 143 of 165 cyw4354 20.1.2 sdio high-speed mode timing sdio high-speed mode timing is shown by the combination of figure 38 and table 53 . figure 38. sdio bus timing (high-speed mode) table 53. sdio bus timing a parameters (high-speed mode) a. timing is based on cl ? 40pf load on cmd and data. parameter symbol minimum typical maximum unit sdio clk (all values are referred to minimum vih and maximum vil b ) b. min. (vih) = 0.7 vddio and max. (vil) = 0.2 vddio. frequency ? data transfer mode fpp 0 ? 50 mhz frequency ? identification mode fod 0 ? 400 khz clock low time twl 7 ? ? ns clock high time twh 7 ? ? ns clock rise time ttlh ? ? 3 ns clock low time tthl ? ? 3 ns inputs: cmd, dat (referenced to clk) ????? input setup time tisu 6 ? ? ns input hold time tih 2 ? ? ns outputs: cmd, dat (referenced to clk) ????? output delay time ? data transfer mode todly ? ? 14 ns output hold time toh 2.5 ? ? ns total system capacitance (each line) cl ? ? 40 pf t wl t wh f pp t thl t isu t tlh t ih t odly input output 50% ? vdd t oh sdio_clk
document number: 002-14809 rev. *j page 144 of 165 cyw4354 20.1.3 sdio bus timing specifications in sdr modes clock timing figure 39. sdio clock timing (sdr modes) table 54. sdio bus clock timing parameters (sdr modes) parameter symbol minimum maximum unit comments ?t clk 40 ? ns sdr12 mode 20 ? ns sdr25 mode 10 ? ns sdr50 mode 4.8 ? ns sdr104 mode ?t cr , t cf ? 0.2 t clk ns t cr , t cf < 2.00 ns (max.) @100 mhz, c card = 10 pf t cr , t cf < 0.96 ns (max.) @208 mhz, c card = 10 pf clock duty? 3070%? t clk t cr sdio_clk t cf t cr
document number: 002-14809 rev. *j page 145 of 165 cyw4354 device input timing figure 40. sdio bus input timing (sdr modes) table 55. sdio bus input timing parameters (sdr modes) symbol minimum maximum unit comments sdr104 mode t is 1.4 ? ns c card = 10 pf, vct = 0.975v t ih 0.80 ? ns c card = 5 pf, vct = 0.975v sdr50 mode t is 3.00 ? ns c card = 10 pf, vct = 0.975v t ih 0.80 ? ns c card = 5 pf, vct = 0.975v t is sdio_clk t ih cmd ? input dat[3:0] ? input
document number: 002-14809 rev. *j page 146 of 165 cyw4354 device output timing figure 41. sdio bus output ti ming (sdr modes up to 100 mhz) figure 42. sdio bus output timing (sdr modes 100 mhz to 208 mhz) table 56. sdio bus output timing parameters (sdr modes up to 100 mhz) symbol minimum maximum unit comments t odly ?7.5nst clk 10 ns c l = 30 pf using driver type b for sdr50 t odly ? 14.0 ns t clk 20 ns c l = 40 pf using for sdr12, sdr25 t oh 1.5 ? ns hold time at the t odly (min.) c l = 15 pf t odly sdio_clk t oh cmd ? input dat[3:0] ? input t clk t op sdio_clk cmd ? input dat[3:0] ? input t clk t odw
document number: 002-14809 rev. *j page 147 of 165 cyw4354 ? t op = +1550 ps for junction temperature of ? t op = 90 degrees during operation ? t op = ?350 ps for junction temperature of ? t op = ?20 degrees during operation ? t op = +2600 ps for junction temperature of ? t op = ?20 to +125 degrees during operation figure 43. ? t op consideration for variable data window (sdr 104 mode) table 57. sdio bus output timing parameters (sdr modes 100 mhz to 208 mhz) symbol minimum maximum unit comments t op 0 2 ui card output phase ? t op ?350 +1550 ps delay variation due to temp change after tuning t odw 0.60 ? ui t odw =2.88 ns @208 mhz 4 t op = 1550 ps sampling point after tuning 4 t op = C350 ps data valid window data valid window data valid window sampling point after card junction heating by +90c from tuning temperature sampling point after card junction cooling by C20c from tuning temperature
document number: 002-14809 rev. *j page 148 of 165 cyw4354 20.1.4 sdio bus timing specifications in ddr50 mode figure 44. sdio clock timing (ddr50 mode) table 58. sdio bus clock timing parameters (ddr50 mode) parameter symbol minimum maximum unit comments ?t clk 20 ? ns ddr50 mode ?t cr ,t cf ? 0.2 tclk ns t cr , t cf < 4.00 ns (max.) @50 mhz, c card = 10 pf clock duty ? 45 55 % ? t clk t cr sdio_clk t cf t cr
document number: 002-14809 rev. *j page 149 of 165 cyw4354 data timing, ddr50 mode figure 45. sdio data timing (ddr50 mode) table 59. sdio bus timing parameters (ddr50 mode) parameter symbol minimum maximum unit comments input cmd input setup time t isu 6?nsc card < 10 pf (1 card) input hold time t ih 0.8 ? ns c card < 10 pf (1 card) output cmd output delay time t odly ?13.7nsc card < 30 pf (1 card) output hold time t oh 1.5 ? ns c card < 15 pf (1 card) input dat input setup time t isu2x 3?nsc card < 10 pf (1 card) input hold time t ih2x 0.8 ? ns c card < 10 pf (1 card) output dat output delay time t odly2x ?7.5nsc card < 25 pf (1 card) output hold time t odly2x 1.5 ? ns c card < 15 pf (1 card) t isu2x sdio_clk dat[3:0] ? input f pp t ih2x t isu2x t ih2x invalid invalid invalid invalid data data data data data data t odly2x ? (min) t odly2x ? (min) t odly2x ? (max) t odly2x ? (max) dat[3:0] ? output in ? ddr50 ? mode, ? dat[3:0] ? lines ? are ? sampled ? on ? both ? edges ? of ? the ? clock ? (not ? applicable ? for ? cmd ? line) available ? timing ? window ? for ? card ? output ? transition available ? timing ? window ? for ? host ? to ? sample ? data ? from ? card
document number: 002-14809 rev. *j page 150 of 165 cyw4354 20.2 hsic interface specifications table 60. hsic interface parameters parameter symbol minimum typical maximum unit comments hsic signaling voltage v dd 1.1 1.2 1.3 v ? i/o voltage input low v il ?0.3 ? 0.35 v dd v? i/o voltage input high v ih 0.65 v dd ?v dd + 0.3 v ? i/o voltage output low v ol ??0.25 v dd v? i/o voltage output high v oh 0.75 v dd ??v? i/o pad drive strength o d 40 ? 60 ? controlled output impedance driver i/o weak keepers i l 20 ? 70 ma ? i/o input impedance z i 100 ? ? k ? ? total capacitive load a a. total capacitive load (c l ), includes device input/output capa citance, and capacitance of a 50 ? pcb trace with a length of 10 cm. c l 3?14pf? characteristic trace impedance t i 45 50 55 ? ? circuit board trace length t l ??10cm? circuit board trace propagation skew b b. maximum propagation delay skew in strobe or data with respect to each other. the tr ace delay should be matched between strobe and data to ensure that the signal timing is wi thin specification limi ts at the receiver. t s ??15ps? strobe frequency c c. jitter and duty cycle are not separately specified paramet ers, they are incorporated into the values in the ta b l e 6 0 . f strobe 239.988 240 240.012 mhz 500 ppm slew rate (rise and fall) strobe and data c t slew 0.60 v dd 1.0 1.2 v/ns averaged from 30% ~ 70% points receiver data setup time (with respect to strobe) c t s 300 ? ? ps measured at the 50% point receiver data hold time (with respect to strobe) c t b 300 ? ? ps measured at the 50% point
document number: 002-14809 rev. *j page 151 of 165 cyw4354 20.3 pci express interface parameters table 61. pci express interface parameters parameter symbol comments minimum typical maximum unit general baud rate bps ? ? 5 ? gbaud reference clock amplitude vref lvpecl 1 ? ? v receiver differential termination zrx-diff-dc differential termination 80 100 120 ? dc impedance zrx-dc dc common-mode impedance 40 50 60 ? powered down termination (pos) zrx-high-imp-dc- pos power-down or reset high impedance 100k ? ? ? powered down termination (neg) zrx-high-imp-dc- neg power-down or reset high impedance 1k ? ? ? input voltage vrx-diffp-p ac coupled, differential p-p 175 ? ? mv jitter tolerance trx-eye minimum receiver eye width 0.4 ? ? ui differential return loss rlrx-dif f differential re turn loss 10 ? ? db common-mode return loss rlrx-c m common-mode return loss 6 ? ? db unexpected electrical idle enter detect threshold integration time trx-idel-det-diff- entertime an unexpected electrical idle must be recognized no longer than this time to signal an unexpected idle condition. ??10ms signal detect threshold vrx-idle-det-diffp- p electrical idle detect threshold 65 ? 175 mv transmitter output voltage vtx-diffp-p di fferential p-p, program- mable in 16 steps 0.8 ? 1200 mv output voltage rise time vtx-rise 20% to 80% 0.125 (2.5 gt/s) 0.15 (5 gt/s) ?? ui output voltage fall time vtx-fall 80% to 20% 0.125 (2.5 gt/s) 0.15 (5 gt/s) ?? ui rx detection voltage swing vtx-rcv-detect the amount of voltage change allowed during receiver detection. ? ? 600 mv tx ac peak common- mode voltage (5 gt/s) vtx-cm-ac-pp tx ac common mode voltage (5 gt/s) ? ? 100 mv tx ac peak common- mode voltage (2.5 gt/s) vtx-cm-ac-p tx ac common mode voltage (2.5 gt/s) ??20mv
document number: 002-14809 rev. *j page 152 of 165 cyw4354 20.4 jtag timing absolute delta of dc common-model voltage during l0 and electrical idle vtx-cm-dc-active- idle-delta absolute delta of dc common-model voltage during l0 and electrical idle. 0 ? 100 mv absolute delta of dc common-model voltage between d+ and d- vtx-cm-dc-line- delta dc offset between d+ and d- 0?25mv electrical idle differential peak output voltage vtx-idle-diff-ac-p peak-to-peak voltage 0 ? 20 mv tx short circuit current itx-short current limit when tx output is shorted to ground. ??90ma dc differential tx termi- nation ztx-diff-dc low impedance defined during signaling (parameter is captured for 5.0 ghz by rltx-diff) 80 ? 120 ? differential return loss rltx-diff differential return loss 10 (min.) for 0.05: 1.25 ghz ?? db common-mode return loss rltx-cm common-mode return loss 6 ? ? db tx eye width ttx-eye minimum tx eye width 0.75 ? ? ui table 62. jtag timing characteristics signal name period output maximum output minimum setup hold tck 125 ns ? ? ? ? tdi ? ? ? 20 ns 0 ns tms ? ? ? 20 ns 0 ns tdo ? 100 ns 0 ns ? ? jtag_trst 250 ns ? ? ? ? table 61. pci express interface parameters (cont.) parameter symbol comments minimum typical maximum unit
document number: 002-14809 rev. *j page 153 of 165 cyw4354 21. power-up sequence and timing 21.1 sequencing of reset and regulator control signals the cyw4354 has two signals that allow the host to control power consumption by enabl ing or disabling the bluetooth, wlan, and internal regulator blocks. these signals are described below. additionally, diagrams are provi ded to indicate proper sequencing of the signals for various operational states (see figure 46 , figure 47 on page 154 , and figure 48 and figure 49 on page 155 ). the timing values indicated are minimum required va lues; longer delays are also acceptable. 21.1.1 description of control signals wl_reg_on : used by the pmu to power up the wlan section. it is also or-gated with the bt_reg_on input to control the internal cyw4354 regulators. when this pin is high, the regulato rs are enabled and the wlan section is out of reset. when this pin is low the wlan section is in reset. if both the bt_reg_o n and wl_reg_on pins are low, the regulators are disabled. bt_reg_on : used by the pmu (or-gated with wl_reg_on) to powe r up the internal cyw4354 regulators. if both the bt_reg_on and wl_reg_on pins are low, the regulators are disabled. when this pin is low and wl_reg_on is high, the bt section is in reset. note: for both the wl_reg_on and bt_reg_on pins, th ere should be at least a 10 ms time del ay between consecutive toggles (where both signals have been driven low). this is to allow time for th e cbuck regulator to discharge. if this delay is not followed, then there may be a vddio in-rush current on the or der of 36 ma during the next pmu cold start. the reset requirements for the bluetooth core are also applicable fo r the fm core. in other words, if fm is to be used, then th e bluetooth core must be enabled. the cyw4354 has an internal power-on reset (por) circuit. the dev ice will be held in reset for a maximum of 110 ms after vddc and vddio have both passed the por threshold. wait at least 15 0 ms after vddc and vddio are available before initiating sdio accesses. vbat should not rise 10%?90% faster than 40 microseconds. vbat should be up before or at the same time as vddio. vddio should not be present first or be held high before vbat is high.
document number: 002-14809 rev. *j page 154 of 165 cyw4354 21.1.2 control signal timing diagrams figure 46. wlan = on, bluetooth = on figure 47. wlan = off, bluetooth = off 32.678 ? khz ? sleep ? clock vbat* vddio wl_reg_on bt_reg_on 90% ? of ? vh ~ ? 2 ? sleep ? cycles *notes: 1. ? vbat ? should ? not ? rise ? 10%?90% ? faster ? than ? 40 ? microseconds. ? 2. ? vbat ? should ? be ? up ? before ? or ? at ? the ? same ? time ? as ? vddio. ? vddio ? should ? not ? be ? present ? first ? or ? be ? held ? high ? before ? vbat ? is ? high. vbat* vddio wl_reg_on bt_reg_on 32.678 ? khz ? sleep ? clock *notes: 1. ? vbat ? should ? not ? rise ? 10%?90% ? faster ? than ? 40 ? microseconds. ? 2. ? vbat ? should ? be ? up ? before ? or ? at ? the ? same ? time ? as ? vddio. ? vddio ? should ? not ? be ? present ? first ? or ? be ? held ? high ? before ? vbat ? is ? high.
document number: 002-14809 rev. *j page 155 of 165 cyw4354 figure 48. wlan = on, bluetooth = off figure 49. wlan = off, bluetooth = on vbat* vddio wl_reg_on bt_reg_on 90% ? of ? vh ~ ? 2 ? sleep ? cycles 32.678 ? khz ? sleep ? clock *notes: 1. ? vbat ? should ? not ? rise ? 10%?90% ? faster ? than ? 40 ? microseconds. ? 2. ? vbat ? should ? be ? up ? before ? or ? at ? the ? same ? time ? as ? vddio. ? vddio ? should ? not ? be ? present ? first ? or ? be ? held ? high ? before ? vbat ? is ? high. vbat* vddio wl_reg_on bt_reg_on 90% ? of ? vh ~ ? 2 ? sleep ? cycles 32.678 ? khz ? sleep ? clock *notes: 1. ? vbat ? should ? not ? rise ? 10%?90% ? faster ? than ? 40 ? microseconds. ? 2. ? vbat ? should ? be ? up ? before ? or ? at ? the ? same ? time ? as ? vddio. ? vddio ? should ? not ? be ? present ? first ? or ? be ? held ? high ? before ? vbat ? is ? high.
document number: 002-14809 rev. *j page 156 of 165 cyw4354 figure 50 shows the wlan boot-up sequence from power-up to firmware download. figure 50. wlan boot-up sequence < ? 950 ? s after ? 8 ? ms ? the ? reference ? clock ? is ? assumed ? to ? be ? up. ?? access ? to ? pll ? registers ? is ? possible. 8 ? ms ? < ? 4 ? ms ? < ? 104 ? ms ? after ? a ? fixed ? delay ? following ? internal ? por ? and ? wl_reg_on ? going ? high, ? the ? device ? responds ? to ? host ? f0 ? (address ? 0x14) ? reads. vddio wl_reg_on vddc (from ? internal ? pmu) internal ? por device ? requests ? for ? reference ? clock host ? interaction: host ? polls ? f0 ? (address ? 0x14) ? until ? it ? reads ? a ? predefined ? pattern. host ? sets ? wake \ up \ wlan ? bit ? and ? waits ? 8 ? ms, ? the ? maximum ? time ? for ? reference ? clock ? availability. after ? 8 ? ms, ? host ? programs ? pll ? registers ? to ? set ? crystal ? frequency host ? downloads ? code. chip ? active ? interrupt ? is ? asserted ? after ? the ? pll ? locks vbat* *notes: 1. ? vbat ? should ? not ? rise ? 10%?90% ? faster ? than ? 40 ? microseconds. ? 2. ? vbat ? should ? be ? up ? before ? or ? at ? the ? same ? time ? as ? vddio. ? vddio ? should ? not ? be ? present ? first ? or ? be ? held ? high ? before ? vbat ? is ? high.
document number: 002-14809 rev. *j page 157 of 165 cyw4354 22. package information 22.1 package thermal characteristics the information in table 63 and ta b l e 6 4 is based on the following conditions: no heat sink, t a = 70c. this is an estimate, based on a 4- layer pcb that conforms to eia/jesd51?7 (101.6 mm 101.6 mm 1.6 mm) and p = 1.53w continuous dissipation. absolute junction temperature limits are maintained through acti ve thermal monitoring and driver-based techniques that may incl ude duty-cycle limiting or turning off one of the tx chains, or both. 22.2 junction temperature estimation and psi jt versus theta jc the package thermal characterization parameter psi jt ( ? jt ) yields a better estimation of actual junction temperature (t j ) than using the junction-to-case thermal resistance parameter theta jc ( jc ). the reason for this is that jc is based on the assumption that all the power is dissipated through the top surface of the package case . in actual applications, however, some of the power is diss ipated through the bottom and sides of the package. ? jt takes into account the power dissipated through the top, bottom, and sides of the package. the equation for calculating the device junction temperature is: t j = t t + p x ? jt where: t j = junction temperature at steady-state condition (c) t t = package case top center temperat ure at steady-stat e condition (c) p = device power dissipation (watts) ? jt = package thermal characteri stics; no airflow (c/w) 22.3 environmental characteristics for environmental char acteristics data, see table 31 on page 103 . table 63. wlcsp package thermal characteristics characteristic wlcsp ja (c/w) (value in still air) 26.86 jb (c/w) 2.23 jc (c/w) 1.09 ? jt (c/w) 2.48 ? jb (c/w) 11.61 maximum junction temperature t j (c) 125 maximum power dissipation (w) 1.53 table 64. wlbga package thermal characteristics characteristic wlbga ja (c/w) (value in still air) 26.80 jb (c/w) 1.66 jc (c/w) 1.16 ? jt (c/w) 1.85 ? jb (c/w) 7.93 maximum junction temperature t j (c) 125 maximum power dissipation (w) 1.53
document number: 002-14809 rev. *j page 158 of 165 cyw4354 23. mechanical information figure 51. 192-ball wlbga pack age mechanical information
document number: 002-14809 rev. *j page 159 of 165 cyw4354 figure 52. wlbga keep-out areas for pcb layout (top view, balls facing down)
document number: 002-14809 rev. *j page 160 of 165 cyw4354 figure 53. 395-bump wlcsp package
document number: 002-14809 rev. *j page 161 of 165 cyw4354 figure 54. wlcsp keep-out areas for pcb layout (top view, balls facing down)
document number: 002-14809 rev. *j page 162 of 165 cyw4354 24. ordering information part number package description operating ambient temperature cyw4354xkubg 192-ball wlbga (4.87 mm 7.67 mm, 0.4 mm pitch) dual-band 2.4 ghz and 5 ghz wlan + bt 4.0 + fmrx ?30c to +85c (?22f to 185f) cyw4354xkwbg 395-bump wlcsp (4.87 mm 7.67 mm, 0.2 mm pitch) dual-band 2.4 ghz and 5 ghz wlan + bt 4.0 + fmrx ?30c to +85c (?22f to 185f) cyw4354zkubg 192-ball wlbga (4.87 mm 7.67 mm, 0.4 mm pitch) dual-band 2.4 ghz and 5 ghz wlan ?30c to +85c (?22f to 185f)
document number: 002-14809 rev. *j page 163 of 165 cyw4354 document history document title: cyw43 54 single-chip 5g wi-fi ieee 802. 11ac 22 mac/baseband/radio with integrated bl uetooth 4.1 and fm receiver document number: 002-14809 revision ecn orig. of change submission date description of change ** ? ? 07/31/13 4354-ds100-r initial release *a ? ? 11/06/13 4354-ds101-r updated: ? section 2: ?power supplies and power management,? on page 27. ? ?wlan power management? on page 29. ? ?crystal interface and clock generation? on page 32. ? table 4: ?crystal oscillator and external clock ? requirements and performance,? on page 33: frequency conditions. ? figure 7: ?startup signaling sequence,? on page 43. ? ?receiver path? on page 88. ? ?transmit path? on page 88. ? section 13: ?pinout and signal descriptions,? on page 89. ? table 29: ?gpio alternative signal functions,? on page 135. ? table 34: ?recommended operating condi tions and dc characteristics,? on page 142: dc supply voltage for digital i/o (minimum value). ? table 42: ?wlan 2.4 ghz receiver performance specifications,? on page 163: siso/mimo rx sensitivity. ? table 46: ?wlan 5 ghz receiver perf ormance specifications,? on page 180: siso/mimo rx sensitivity. ? table 51: ?ldo3p3 specifications,? on page 192. ? table 57: ?typical wlan power consumption,? on page 199. ? table 58: ?bluetooth ble and fm current consumption,? on page 201. ? section 22: ?package information,? on page 219. ? section 23: ?mechanical information,? on page 221. ? section 24: ?ordering information,? on page 226. added: ? figure 4: ?typical power topology for the cyw435x,? on page 28. ? ?external 32.768 khz low-power oscillator? on page 35. ? table 30: ?gpio status vs. test modes,? on page 136. ? table 52: ?ldo3p3_b specifications,? on page 193. *b ?? 12/12/13 4354-ds102-r updated: ? the cyw4354 now supports pci express base specification v3.0 running at gen1 speeds. ? ?wlan 2.4 ghz receiver performance specifications? on page 158: note update. ? ?wlan 2.4 ghz transmitter performance specifications? on page 170: note update. ? ?wlan 5 ghz receiver performance specifications? on page 174: note update. ? ?wlan 5 ghz transmitter performance specifications? on page 187: note update. ? ?package thermal characteristics? on page 219: note update. section 24: ?ordering information,? on page 227. *c ?? 12/20/13 4354-ds103-r updated: ? table 33: ?environmental ratings,? on page 141: ambient temperature range for functional operation is now ?30c to +85c.
document number: 002-14809 rev. *j page 164 of 165 cyw4354 *d ?? 03/24/14 4354-ds104-r updated: ? table 4: ?external 32.768 khz sleep clock specifications,? on page 28 ? figure 33: ?wlbga ball map, 4.87 7.67 array, 192-balls, a7?v12 (bottom view ? balls facing up),? on page 83 ? table 20: ?395-bump wlcsp coordinates,? on page 90 (modified bump 230, see note at end of the table 20.) ? table 32: ?bluetooth receiver rf s pecifications,? on page 129 (footnotes modified) table 50: ?bluetooth ble and fm current consumption,? on page 167 *e ?? 04/02/14 4354-ds105-r updated: ? table 4: ?external 32.768 khz sleep clock specifications,? on page 28 ? figure 34: ?wlbga ball map, 4.87 7.67 array, 192-ball, a7?v12 (bottom view ? balls facing up),? on page 84 ? table 49: ?bluetooth ble and fm current consumption,? on page 164 ? ?receiver path? on page 80 ? figure 32: ?radio functional block diagram (core 0),? on page 81 ? table 38: ?wlan 2.4 ghz receiver pe rformance specifications,? on page 139 ? table 39: ?wlan 2.4 ghz transmitter performance specifications,? on page 145 ? table 40: ?wlan 5 ghz receiver perf ormance specifications,? on page 147 ? table 41: ?wlan 5 ghz transmitter performance specifications,? on page 154 ? general spurious emissions specifications (deleted) *f ?? 05/20/14 4354-ds106-r updated: section 24: ?ordering information,? on page 189. *g ?? 06/30/14 4354-ds107-r updated: ? ?cyw4354 pmu features? on page 22 ? figure 3: ?typical power topology for the cyw4354,? on page 23 ? table 18: ?pin list by pin number (192-pin wlbga package),? on page 85 ? table 19: ?pin list by pin name (192-pin wlbga package),? on page 88 ? table 20: ?395-bump wlcsp coordinates,? on page 91 ? table 21: ?wlcsp signal descriptions,? on page 102 ? table 60: ?pci express interface parameters,? on page 175 added: ? ?electrostatic discharge specifications? on page 124 *h ?? 08/08/14 4354-ds108-r updated: changed document type from ?preliminary data sheet? to ?data sheet?. *i ?? 10/15/14 4354-ds109-r updated: ? ?i/o states? on page 99. figure 52: ?wlbga keep-out areas for pcb layout (top view, balls facing down),? on page 159. *j 5451155 utsv 09/28/16 converted to cypress template document title: cyw43 54 single-chip 5g wi-fi ieee 802. 11ac 22 mac/baseband/radio with integrated bl uetooth 4.1 and fm receiver document number: 002-14809
document number: 002-14809 rev. *j revised september 28, 2016 page 165 of 165 cyw4354 ? cypress semiconductor corporation, 2013-2016. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc (?cypress?). this document, including any software or firmware included or referenced in this document (?software?), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragra ph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a written agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hard ware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modi fication, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the im plied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information pr ovided in this document, includ ing any sample design informati on or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear in stallations, life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury , death, or property damage (?unintended uses?). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community forums | wiced iot forums | projects | video | blogs | training | components technical support cypress.com/support 165

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